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    SECURE DEVICE POWER-UP APPARATUS AND METHOD
    12.
    发明申请
    SECURE DEVICE POWER-UP APPARATUS AND METHOD 有权

    公开(公告)号：US20220198022A1

    公开(公告)日：2022-06-23

    申请号：US17132844

    申请日：2020-12-23

    Applicant: Intel Corporation

    Inventor： Sagar C. Pawar ,  Pannerkumar Rajagopal ,  Raghavendra N ,  Prakash Pillai ,  Ovais Pir

    IPC: G06F21/57 ,  G06F1/18 ,  G06F21/32 ,  G06F1/3215 ,  G06F1/26

    Abstract: A power-up scheme for a computing system that applies a biometric sensor (e.g., a fingerprint sensor, eye sensor, etc.) to authenticate a user before enabling power-up of the computing system or to resume transition to a power state (e.g., one of the power states defined by the Advance Configuration and Power Interface (ACPI)). Output of the biometric sensor is compared against data of a registered user for a match. The data may include an original copy of an output of the biometric sensor saved in a non-volatile memory (e.g., serial peripheral interface (SPI) flash device). If a match exists, a logic in the computing system will allow the computing system to power-up. In the absence of a match, the computing system will not be powered up. In some examples, battery charging is also disabled if the match is not found.

    TECHNOLOGIES FOR ACHIEVING SYNCHRONIZED OVERCLOCKING SETTING ON MULTIPLE COMPUTING DEVICES
    13.
    发明申请
    TECHNOLOGIES FOR ACHIEVING SYNCHRONIZED OVERCLOCKING SETTING ON MULTIPLE COMPUTING DEVICES 审中-公开

    公开(公告)号：US20200125579A1

    公开(公告)日：2020-04-23

    申请号：US16426029

    申请日：2019-05-30

    Applicant: Intel Corporation

    Inventor： Sagar C. Pawar ,  Prakash Pillai ,  Raghavendra N ,  Aneesh A. Tuljapurkar

    IPC: G06F16/27 ,  G06F1/04 ,  H04J3/06 ,  G06F1/3296 ,  G06F1/324 ,  G06F1/12

    Abstract: Technologies for synchronized overclocking setting between multiple networked computing devices include a master computing device and multiple slave computing devices communicating over a network. The master computing device establishes a connection with the slave computing devices. Establishing the connection may include synchronizing the slave computing devices with a master time clock of the master computing device. The master computing device determines its own overclocking setting and requests overlocking settings from the slave computing devices. The overclocking settings may include processor frequency, processor voltage, or other overclocking parameters. The master computing device determines a best overclocking setting from its own overclocking setting and the overclocking settings received from the slave computing device. The master computing device advertises the best overclocking setting to the slave computing devices. The slave computing devices may implement the best overclocking setting. Other embodiments are described and claimed.

    Wirelessly providing power to a fully discharged battery
    14.
    发明授权
    Wirelessly providing power to a fully discharged battery 有权

    公开(公告)号：US10516285B2

    公开(公告)日：2019-12-24

    申请号：US14725586

    申请日：2015-05-29

    Applicant: INTEL CORPORATION

    Inventor： Sagar C. Pawar ,  Prakash Pillai

    IPC: H02J7/02 ,  H02J50/80 ,  H02J50/10 ,  H02J7/04

    Abstract: Techniques for wireless charging in a system, method, and apparatus are described herein. An apparatus for charging at a wireless power receiver may include logic. The logic is configured to supply voltage received at the wireless power receiver at a first power level to a battery that is initially fully discharged, wherein the power of the first power level is received during a predefined interval of a fully discharged battery protocol. The logic is to monitor a second power level available at the battery, and initiate a wireless handshake with a wireless power transmitter inductively coupled to the wireless power receiver indicating configurations of the wireless power receiver upon detection of the second power level meeting or exceeding a predefined threshold.

    Power management of a processor and a platform in active state and low power state
    16.
    发明授权
    Power management of a processor and a platform in active state and low power state 有权

    公开(公告)号：US12007823B2

    公开(公告)日：2024-06-11

    申请号：US17702504

    申请日：2022-03-23

    Applicant: Intel Corporation

    Inventor： Pannerkumar Rajagopal ,  Raghavendra N ,  Ovais Pir ,  Prakash Pillai ,  Sagar C. Pawar

    IPC: G06F1/32 ,  G06F1/3231

    CPC classification number: G06F1/3231

    Abstract: A power-management scheme where when a system-on-chip (SoC) is in an active state, control and monitoring logic or circuitry turns off all wake logic or circuits for various associated intellectual property (IP) blocks. Based on user defined operating system power manager (OSPM) policies, OSPM kicks off an interrupt to the control and monitoring logic or circuitry to turn off or power gate the wake logic for individual IP blocks in the SoC. As such, wake logic that are idle in active state (e.g., S0 state) and would otherwise draw power in the S0 state are now turned off, thus saving power and/or extending battery life for the system. When the SoC is in a low power state, then the control and monitoring logic or circuitry selectively turns on the wake logic for the associated IP blocks based on detected user presence for the computing system having the SoC.

    CONTROL OF POWER STATE IN COMPUTER PROCESSOR
    17.
    发明公开
    CONTROL OF POWER STATE IN COMPUTER PROCESSOR 审中-公开

    公开(公告)号：US20240004454A1

    公开(公告)日：2024-01-04

    申请号：US17809652

    申请日：2022-06-29

    Applicant: Intel Corporation

    Inventor： Sagar C. Pawar ,  Pannerkumar Rajagopal ,  Raghavendra Nagaraj ,  Ovais F. Pir ,  Prakash Pillai

    IPC: G06F1/3296 ,  G06F1/30

    CPC classification number: G06F1/3296 ,  G06F1/30

    Abstract: In an embodiment, a processor may include processing circuits to execute instructions. The processor may also include at least one circuit to: detect a management mode trigger event during operation of the processor in a first power state, the management mode trigger event to initiate a management mode in the processor; in response to a detection of the management mode trigger event, switch the processor from the first power state to a second power state; and after a switch of the processor from the first power state to the second power state, initiate the management mode in the processor. Other embodiments are described and claimed.

    POWER MANAGEMENT OF A PROCESSOR AND A PLATFORM IN ACTIVE STATE AND LOW POWER STATE
    19.
    发明申请
    POWER MANAGEMENT OF A PROCESSOR AND A PLATFORM IN ACTIVE STATE AND LOW POWER STATE 有权

    公开(公告)号：US20220391003A1

    公开(公告)日：2022-12-08

    申请号：US17702504

    申请日：2022-03-23

    Applicant: Intel Corporation

    Inventor： Pannerkumar Rajagopal ,  Raghavendra N ,  Ovais Pir ,  Prakash Pillai ,  Sagar C. Pawar

    IPC: G06F1/3231

    Abstract: A power-management scheme where when a system-on-chip (SoC) is in an active state, control and monitoring logic or circuitry turns off all wake logic or circuits for various associated intellectual property (IP) blocks. Based on user defined operating system power manager (OSPM) policies, OSPM kicks off an interrupt to the control and monitoring logic or circuitry to turn off or power gate the wake logic for individual IP blocks in the SoC. As such, wake logic that are idle in active state (e.g., S0 state) and would otherwise draw power in the S0 state are now turned off, thus saving power and/or extending battery life for the system. When the SoC is in a low power state, then the control and monitoring logic or circuitry selectively turns on the wake logic for the associated IP blocks based on detected user presence for the computing system having the SoC.

    DYNAMIC ADJUSTMENT OF AUDIO PRODUCTION
    20.
    发明申请
    DYNAMIC ADJUSTMENT OF AUDIO PRODUCTION 有权
    动态调整音像制作

    公开(公告)号：US20160364207A1

    公开(公告)日：2016-12-15

    申请号：US14739954

    申请日：2015-06-15

    Applicant: Intel Corporation

    Inventor： Sagar C. Pawar ,  Prakash Pillai

    IPC: G06F3/16

    CPC classification number: G06F3/165

    Abstract: Apparatuses, methods, and computer-readable media for dynamic configuration of audio production are described. Audio production nodes (“APNs”) may produce audio. The APNs and may be configured to be compliant with a Precision Time Protocol (“PTP”). The APNs may be configured to perform dynamic configuration of audio production. An APN may receive configuration-related information transmitted from one or more other APNs, such as in association with operation of the PTP. An APN, in response to receipt of this configuration-related data, may modify configuration settings used for its audio production such as modification of timing, tone, power, intensity, equalization settings, or other configuration settings. The APN may be configured to produce its own configuration-related data for use by other APNs to modify the other APNs' configuration settings. Other embodiments may be described and/or claimed.

    Abstract translation: 描述了用于音频制作的动态配置的装置，方法和计算机可读介质。 音频制作节点（“APN”）可能产生音频。 APN并且可以被配置为符合精确时间协议（“PTP”）。 APN可以被配置为执行音频制作的动态配置。 APN可以接收从一个或多个其他APN发送的配置相关信息，例如与PTP的操作相关联。 响应于接收到该配置相关数据，APN可以修改用于其音频制作的配置设置，例如修改定时，音调，功率，强度，均衡设置或其他配置设置。 APN可以被配置为产生其自己的配置相关数据，供其他APN使用以修改其他APN的配置设置。 可以描述和/或要求保护其他实施例。

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