公开(公告)号：US20240267334A1

公开(公告)日：2024-08-08

申请号：US18621516

申请日：2024-03-29

Applicant: Intel Corporation

Inventor： Stephen Palermo ,  Bradley Chaddick ,  Gage Eads ,  Mrittika Ganguli ,  Abhishek Khade ,  Abhirupa Layek ,  Sarita Maini ,  Niall McDonnell ,  Rahul Shah ,  Shrikant Shah ,  William Burroughs ,  David Sonnier

IPC: H04L47/125 ,  H04L47/62 ,  H04L47/625 ,  H04L47/6275

CPC classification number: H04L47/125 ,  H04L47/62 ,  H04L47/624 ,  H04L47/6255 ,  H04L47/6275

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for dynamic load balancing for multi-core computing environments. An example apparatus includes a first and a plurality of second cores of a processor, and circuitry in a die of the processor separate from the first and the second cores, the circuitry to enqueue identifiers in one or more queues in the circuitry associated with respective ones of data packets of a packet flow, allocate one or more of the second cores to dequeue first ones of the identifiers in response to a throughput parameter of the first core not satisfying a throughput threshold to cause the one or more of the second cores to execute one or more operations on first ones of the data packets, and provide the first ones to one or more data consumers to distribute the first data packets.

公开(公告)号：US10025746B2

公开(公告)日：2018-07-17

申请号：US14578395

申请日：2014-12-20

Applicant: Intel Corporation

Inventor： William R. Halleck ,  Rahul Shah ,  Venkatraman Iyer

IPC: G06F13/42 ,  G06F13/22

Abstract: A signal is received, a boundary of which is to be sent in alignment with a sync counter value. A nominal latency of a link is determined based on the sync counter value. Additional latency is applied to the signal to increase the nominal latency to a target latency for the link.

公开(公告)号：US09910809B2

公开(公告)日：2018-03-06

申请号：US14578175

申请日：2014-12-19

Applicant: Intel Corporation

Inventor： William R. Halleck ,  Rahul Shah ,  Venkatraman Iyer

IPC: G06F13/40 ,  G06F13/42

CPC classification number: G06F13/4027 ,  G06F13/124 ,  G06F13/1678 ,  G06F13/4282

Abstract: A supersequence is sent to another device to indicate a transition from a partial width link state to another active link state. The supersequence is to be sent over one or more lanes of a link and is to include at least a portion of a start of data sequence (SDS) to include a predefined sequence and a byte number value. The byte number value is to indicate a number of bytes measured from a preceding control interval.

公开(公告)号：US20220286399A1

公开(公告)日：2022-09-08

申请号：US17637416

申请日：2020-09-11

Applicant: Intel Corporation

Inventor： Niall McDonnell ,  Gage Eads ,  Mrittika Ganguli ,  Chetan Hiremath ,  John Mangan ,  Stephen Palermo ,  Bruce Richardson ,  Edwin Verplanke ,  Praveen Mosur ,  Bradley Chaddick ,  Abhishek Khade ,  Abhirupa Layek ,  Sarita Maini ,  Rahul Shah ,  Shrikant Shah ,  William Burroughs ,  David Sonnier

IPC: H04L47/125 ,  H04L47/625 ,  H04L47/62 ,  H04L47/6275

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for hardware queue scheduling for multi-core computing environments. An example apparatus includes a first core and a second core of a processor, and circuitry in a die of the processor, at least one of the first core or the second core included in the die, the at least one of the first core or the second core separate from the circuitry, the circuitry to enqueue an identifier to a queue implemented with the circuitry, the identifier associated with a data packet, assign the identifier in the queue to a first core of the processor, and in response to an execution of an operation on the data packet with the first core, provide the identifier to the second core to cause the second core to distribute the data packet.

公开(公告)号：US10216661B2

公开(公告)日：2019-02-26

申请号：US15821401

申请日：2017-11-22

Applicant: Intel Corporation

Inventor： Venkatraman Iyer ,  Darren S. Jue ,  Rahul Shah ,  Arvind Kumar

IPC: G06F9/30 ,  G06F13/22 ,  G06F12/0831 ,  G06F13/42 ,  G06F8/71 ,  G06F8/77 ,  G06F12/0806 ,  H04L12/933 ,  G06F9/46 ,  G06F13/40 ,  G06F12/0813 ,  G06F12/0815 ,  G06F9/445 ,  G06F1/3287 ,  G06F11/10 ,  H04L9/06 ,  G06F12/0808 ,  H04L12/741 ,  G06F8/73 ,  H04L12/46

Abstract: A serial data link is to be adapted during initialization of the link. Adaptation of the link is to include receiving a pseudorandom binary sequence (PRBS) from a remote agent, analyzing the PRBS to identify characteristics of the data link, and generating metric data describing the characteristics.

公开(公告)号：US20160179740A1

公开(公告)日：2016-06-23

申请号：US14578395

申请日：2014-12-20

Applicant: Intel Corporation

Inventor： William R. Halleck ,  Rahul Shah ,  Venkatraman Iyer

IPC: G06F13/42 ,  G06F13/22

CPC classification number: G06F13/4221 ,  G06F13/22

Abstract: A signal is received, a boundary of which is to be sent in alignment with a sync counter value. A nominal latency of a link is determined based on the sync counter value. Additional latency is applied to the signal to increase the nominal latency to a target latency for the link.

Abstract translation: 接收信号，其边界将与同步计数器值对准发送。 基于同步计数器值确定链路的标称等待时间。 对信号应用额外的延迟，以将标称延迟增加到链路的目标延迟。