公开(公告)号：US20190121414A1

公开(公告)日：2019-04-25

申请号：US16162303

申请日：2018-10-16

Applicant: Intel Corporation

Inventor： Jonathan M. Eastep ,  Richard J. Greco

IPC: G06F1/3203 ,  G06F1/18 ,  G06F9/48 ,  G06F9/50

Abstract: Methods and apparatus to provide holistic global performance and power management are described. In an embodiment, logic (e.g., coupled to each compute node of a plurality of compute nodes) causes determination of a policy for power and performance management across the plurality of compute nodes. The policy is coordinated across the plurality of compute nodes to manage a job to one or more objective functions, where the job includes a plurality of tasks that are to run concurrently on the plurality of compute nodes. Other embodiments are also disclosed and claimed.

公开(公告)号：US09477533B2

公开(公告)日：2016-10-25

申请号：US14583254

申请日：2014-12-26

Applicant: Intel Corporation

Inventor： Jonathan M. Eastep ,  Ilya Sharapov ,  Rob F. Van Der Wijngaart ,  Richard J. Greco ,  Steve S. Sylvester ,  David N. Lombard

IPC: G06F9/52 ,  G06F9/50

CPC classification number: G06F9/522 ,  G06F9/5083 ,  G06F9/5094 ,  G06F2209/508 ,  Y02D10/22

Abstract: Systems and methods may provide a set of cores capable of parallel execution of threads. Each of the cores may run code that is provided with a progress meter that calculates the amount of work remaining to be performed on threads as they run on their respective cores. The data may be collected continuously, and may be used to alter the frequency, speed or other operating characteristic of the cores as well as groups of cores. The progress meters may be annotated into existing code.

Abstract translation: 系统和方法可以提供能够并行执行线程的一组核心。 每个核心可以运行提供有进度计的代码，该进度计算器在线程在其各自的内核上运行时计算待执行的剩余工作量。 可以连续收集数据，并且可以用于改变核心以及核心组的频率，速度或其他操作特性。 进度表可以注释到现有代码中。

公开(公告)号：US20160188380A1

公开(公告)日：2016-06-30

申请号：US14583254

申请日：2014-12-26

Applicant: Intel Corporation

Inventor： Jonathan M. Eastep ,  Ilya Sharapov ,  Rob F. Van Der Wijngaart ,  Richard J. Greco ,  Steve S. Sylvester ,  David N. Lombard

IPC: G06F9/52 ,  G06F9/50

CPC classification number: G06F9/522 ,  G06F9/5083 ,  G06F9/5094 ,  G06F2209/508 ,  Y02D10/22

Abstract: Systems and methods may provide a set of cores capable of parallel execution of threads. Each of the cores may run code that is provided with a progress meter that calculates the amount of work remaining to be performed on threads as they run on their respective cores. The data may be collected continuously, and may be used to alter the frequency, speed or other operating characteristic of the cores as well as groups of cores. The progress meters may be annotated into existing code.

Abstract translation: 系统和方法可以提供能够并行执行线程的一组核心。 每个核心可以运行提供有进度计的代码，该进度计算器在线程在其各自的内核上运行时计算待执行的剩余工作量。 可以连续收集数据，并且可以用于改变核心以及核心组的频率，速度或其他操作特性。 进度表可以注释到现有代码中。

公开(公告)号：US09213390B2

公开(公告)日：2015-12-15

申请号：US13730074

申请日：2012-12-28

Applicant: Intel Corporation

Inventor： Eugene Gorbatov ,  Paul S. Diefenbaugh ,  John H. Crawford ,  Anil K. Kumar ,  Richard J. Greco

IPC: G06F1/32

CPC classification number: G06F1/3206 ,  G06F1/3228 ,  G06F1/3287 ,  Y02D10/171 ,  Y02D50/20

Abstract: Methods and systems may provide for determining a latency constraint associated with a platform and determine an idle window based on the latency constraint. In addition, a plurality of devices on the platform may be instructed to cease one or more activities during the idle window. In one example, the platform is placed in a sleep state during the idle window.

Abstract translation: 方法和系统可以提供用于确定与平台相关联的等待时间约束，并且基于等待时间约束来确定空闲窗口。 此外，可以指示平台上的多个设备在空闲窗口期间停止一个或多个活动。 在一个示例中，平台在空闲窗口期间处于睡眠状态。

公开(公告)号：US10884471B2

公开(公告)日：2021-01-05

申请号：US16162303

申请日：2018-10-16

Applicant: Intel Corporation

Inventor： Jonathan M. Eastep ,  Richard J. Greco

IPC: G06F1/3203 ,  G06F9/48 ,  G06F9/50 ,  G06N20/00 ,  G06F1/329 ,  G06F9/38 ,  G06F9/52

Abstract: Methods and apparatus to provide holistic global performance and power management are described. In an embodiment, logic (e.g., coupled to each compute node of a plurality of compute nodes) causes determination of a policy for power and performance management across the plurality of compute nodes. The policy is coordinated across the plurality of compute nodes to manage a job to one or more objective functions, where the job includes a plurality of tasks that are to run concurrently on the plurality of compute nodes. Other embodiments are also disclosed and claimed.

公开(公告)号：US20180067533A1

公开(公告)日：2018-03-08

申请号：US15689646

申请日：2017-08-29

Applicant: INTEL CORPORATION

Inventor： Federico Ardanaz ,  Jonathan M. Eastep ,  Richard J. Greco ,  Ramkumar Nagappan ,  Alan B. Kyker

IPC: G06F1/32

CPC classification number: G06F1/325 ,  G06F1/3287 ,  G06F1/3293 ,  Y02D10/122 ,  Y02D10/171

Abstract: Apparatus, systems, and methods provide an interface between a plurality of hardware resources of a node and a power manager. The interface is configured to define one or more resource groups to expose to the power manager for power measurement and control, assign the plurality of hardware resources to the one or more resource groups, and provide a power allowance to each resource group.

公开(公告)号：US20180059768A1

公开(公告)日：2018-03-01

申请号：US15788195

申请日：2017-10-19

Applicant: INTEL CORPORATION

Inventor： Jonathan M. Eastep ,  Rohit Banerjee ,  Richard J. Greco ,  Ilya Sharapov ,  David N. Lombard ,  Hari K. Nagpal

IPC: G06F1/32

CPC classification number: G06F1/3234 ,  G06F1/3206

Abstract: Apparatus, systems, and methods provide dynamic spatial power steering among a plurality of power domains in the computer system on a per phase basis of a particular application. Dynamic spatial power steering may include, for example, determining a plurality of phases corresponding to an application comprising tasks for execution on a processing node. determining a spatial power distribution between a plurality of power domains on the processing node based on a performance metric for each phase, monitoring the application to detect a current phase, and applying the spatial power distribution correspond to the current phase to the plurality of power domains.

公开(公告)号：US20170285710A1

公开(公告)日：2017-10-05

申请号：US15088531

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Federico Ardanaz ,  Ian M. Steiner ,  Jonathan M. Eastep ,  Richard J. Greco ,  Krishnakanth V. Sistla ,  Micah Barany ,  Andrew J. Herdrich

IPC: G06F1/28

CPC classification number: G06F1/28 ,  G06F1/3287

Abstract: Apparatus and methods may provide for subscribing a thread to a resource monitor through a machine specific register and subscribing the thread to a class of service through the machine specific register. The resource monitor or the class of service for the thread may be changed without interrupting the thread. The power allocated to the processor core may be changed based on the selected class of service for the thread.

公开(公告)号：US20170277576A1

公开(公告)日：2017-09-28

申请号：US15081424

申请日：2016-03-25

Applicant: Intel Corporation

Inventor： Stephanie Labasan ,  Federico Ardanaz ,  Jonathan M. Eastep ,  Richard J. Greco

IPC: G06F9/50

CPC classification number: G06F9/5083

Abstract: Systems, apparatuses and methods may provide for obtaining, by a system level reallocator in a plurality of reallocators arranged in a hierarchical tree, resource budget information. Additionally, application performance information may be obtained by at least one of the plurality of reallocators. Moreover, a performance imbalance between a plurality of compute subtrees associate with the application performance information may be reduced by the at least one of the plurality of reallocators and based at least in part on the resource budget information and the application performance information.

公开(公告)号：US09720827B2

公开(公告)日：2017-08-01

申请号：US14541504

申请日：2014-11-14

Applicant: Intel Corporation

Inventor： Avinash Sodani ,  Robert J. Kyanko ,  Richard J. Greco ,  Andreas Kleen ,  Milind B. Girkar ,  Christopher M. Cantalupo

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F12/06 ,  G06F12/02

CPC classification number: G06F12/0646 ,  G06F12/023 ,  G06F2212/283

Abstract: In one embodiment, a processor comprises: at least one core formed on a die to execute instructions; a first memory controller to interface with an in-package memory; a second memory controller to interface with a platform memory to couple to the processor; and the in-package memory located within a package of the processor, where the in-package memory is to be identified as a more distant memory with respect to the at least one core than the platform memory. Other embodiments are described and claimed.