公开(公告)号：US20230127749A1

公开(公告)日：2023-04-27

申请号：US18086308

申请日：2022-12-21

Applicant: Intel Corporation

Inventor： Shawna M. Liff ,  Adel A. Elsherbini ,  Johanna M. Swan ,  Arun Chandrasekhar

IPC: H01L23/00 ,  H01L25/18 ,  H01L25/00

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.

公开(公告)号：US20220399324A1

公开(公告)日：2022-12-15

申请号：US17344348

申请日：2021-06-10

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Adel A. Elsherbini ,  Kimin Jun ,  Johanna M. Swan ,  Shawna M. Liff ,  Sathya Narasimman Tiagaraj ,  Gerald S. Pasdast ,  Aleksandar Aleksov ,  Feras Eid

IPC: H01L25/00 ,  H01L25/065 ,  H01L23/00

Abstract: A die assembly comprising: a first component layer having conductive through-connections in an insulator, a second component layer comprising a die, and an active device layer (ADL) at an interface between the first component layer and the second component layer. The ADL comprises active elements electrically coupled to the first component layer and the second component layer. The die assembly further comprises a bonding layer electrically coupling the ADL to the second component layer. In some embodiments, the die assembly further comprises another ADL at another interface between the first component layer and a package support opposite to the interface. The first component layer may comprise another die having through-substrate vias (TSVs). The die and the another die may be fabricated using different process nodes.

公开(公告)号：US20220399294A1

公开(公告)日：2022-12-15

申请号：US17347394

申请日：2021-06-14

Applicant: Intel Corporation

Inventor： Georgios Dogiamis ,  Qiang Yu ,  Adel A. Elsherbini ,  Shawna M. Liff

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/538 ,  H01L25/00

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a die-level interposer having a first surface and an opposing second surface; a first die coupled to the first surface of the die-level interposer by a first hybrid bonding region having a first pitch; a second die coupled to the second surface of the die-level interposer by a second hybrid bonding region having a second pitch different from the first pitch; and a third die coupled to the second surface of the die-level interposer by a third hybrid bonding region having a third pitch different from the first and second pitches.

公开(公告)号：US20220399277A1

公开(公告)日：2022-12-15

申请号：US17345969

申请日：2021-06-11

Applicant: INTEL CORPORATION

Inventor： Adel A. Elsherbini ,  Scott E. Siers ,  Sathya Narasimman Tiagaraj ,  Gerald S. Pasdast ,  Zhiguo Qian ,  Kalyan C. Kolluru ,  Vivek Kumar Rajan ,  Shawna M. Liff ,  Johanna M. Swan

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H01L21/48 ,  H01L25/00

Abstract: An Integrated Circuit (IC), comprising a first conductive trace on a first die, a second conductive trace on a second die, and a conductive pathway electrically coupling the first conductive trace with the second conductive trace. The second die is coupled to the first die with interconnects. The conductive pathway comprises a portion of the interconnects located proximate to a periphery of a region in the first die through which the first conductive trace is not routable. In some embodiments, the conductive pathway reroutes electrical connections away from the region. The region comprises a high congestion zone having high routing density in some embodiments. In other embodiments, the region comprises a “keep-out” zone.

公开(公告)号：US11421376B2

公开(公告)日：2022-08-23

申请号：US16072165

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Shawna M. Liff ,  Feras Eid ,  Aleksandar Aleksov ,  Sasha N. Oster ,  Baris Bicen ,  Thomas L. Sounart ,  Valluri R. Rao ,  Johanna M. Swan

IPC: H01L41/047 ,  D06M10/06 ,  D06M11/46 ,  D06M11/47 ,  H01L41/316 ,  D06M17/00 ,  H01L41/087 ,  D06M11/83 ,  H01L41/187 ,  H01L41/29 ,  D01F11/00

Abstract: Embodiments of the invention include an active fiber with a piezoelectric layer that has a crystallization temperature that is greater than a melt or draw temperature of the fiber and methods of forming such active fibers. According to an embodiment, a first electrode is formed over an outer surface of a fiber. Embodiments may then include depositing a first amorphous piezoelectric layer over the first electrode. Thereafter, the first amorphous piezoelectric layer may be crystallized with a pulsed laser annealing process to form a first crystallized piezoelectric layer. In an embodiment, the pulsed laser annealing process may include exposing the first amorphous piezoelectric layer to radiation from an excimer laser with an energy density between approximately 10 and 100 mJ/cm2 and pulse width between approximately 10 and 50 nanoseconds. Embodiments may also include forming a second electrode over an outer surface of the crystallized piezoelectric layer.

公开(公告)号：US20220230964A1

公开(公告)日：2022-07-21

申请号：US17716229

申请日：2022-04-08

Applicant: Intel Corporation

Inventor： Shawna M. Liff ,  Adel A. Elsherbini ,  Johanna M. Swan

IPC: H01L23/538 ,  H01L25/065

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a first die comprising a first face and a second face; and a second die, the second die comprising a first face and a second face, wherein the second die further comprises a plurality of first conductive contacts at the first face and a plurality of second conductive contacts at the second face, and the second die is between first-level interconnect contacts of the microelectronic assembly and the first die.

公开(公告)号：US20220216182A1

公开(公告)日：2022-07-07

申请号：US17706156

申请日：2022-03-28

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Amr Elshazly ,  Arun Chandrasekhar ,  Shawna M. Liff ,  Johanna M. Swan

IPC: H01L25/065 ,  H01L23/498 ,  H01L25/00

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate, a first die coupled to the package substrate with first interconnects, and a second die coupled to the first die with second interconnects, wherein the second die is coupled to the package substrate with third interconnects, a communication network is at least partially included in the first die and at least partially included in the second die, and the communication network includes a communication pathway between the first die and the second die.

公开(公告)号：US11380624B2

公开(公告)日：2022-07-05

申请号：US16651949

申请日：2017-09-30

Applicant: Intel Corporation

Inventor： Feras Eid ,  Henning Braunisch ,  Shawna M. Liff ,  Georgios C. Dogiamis ,  Johanna M. Swan

IPC: H01L23/552 ,  H01L21/48 ,  H01L23/04 ,  H01L23/10 ,  H01L23/498 ,  H01L23/00

Abstract: A device package and a method of forming the device package are described. The device package includes a substrate having a ground plane and dies disposed on the substrate. The dies are electrically coupled to the substrate with solder balls or bumps surrounded by an underfill layer. The device package has a mold layer disposed over and around the dies, the underfill layer, and the substrate. The device package further includes an additively manufactured electromagnetic interference (EMI) shield layer disposed on an outer surface of the mold layer. The additively manufactured EMI shield layer is electrically coupled to the ground plane of the substrate. The outer surface of the mold layer may include a topmost surface and one or more sidewalls that are covered with the additively manufactured EMI shield layer. The additively manufactured EMI shield may include a first and second additively manufactured EMI shield layers and an additively manufactured EMI shield frame.

公开(公告)号：US20220199453A1

公开(公告)日：2022-06-23

申请号：US17132372

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Michael J. Baker ,  Shawna M. Liff ,  Hsin-Wei Wang ,  Albert S. Lopez

IPC: H01L21/683 ,  H01L21/67 ,  H01L23/00

Abstract: Described herein are carrier assemblies, and related devices and methods. In some embodiments, a carrier assembly includes a carrier; a textured material including texturized microstructures coupled to the carrier; and microelectronic components mechanically coupled to the texturized microstructures. In some embodiments, a carrier assembly includes a carrier having a front side and a back side; an electrode on the front side of the carrier; a dielectric material on the electrode; a charging contact on the back side coupled to the electrode; and microelectronic components electrostatically coupled to the front side of the carrier. In some embodiments, a carrier assembly includes a carrier having a front side and a back side; electrodes on the front side; a dielectric material including texturized microstructures on the electrodes; charging contacts on the back side coupled to the plurality of electrodes; and microelectronic components mechanically and electrostatically coupled to the front side of the carrier.

公开(公告)号：US20220189861A1

公开(公告)日：2022-06-16

申请号：US17121093

申请日：2020-12-14

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Mohammad Enamul Kabir ,  Adel A. Elsherbini ,  Shawna M. Liff ,  Johanna M. Swan ,  Feras Eid

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/538

Abstract: Disclosed herein are microelectronic assemblies including microelectronic components coupled by direct bonding, and related structures and techniques. In some embodiments, a microelectronic assembly may include a first microelectronic component including a first guard ring extending through at least a portion of a thickness of and along a perimeter; a second microelectronic component including a second guard ring extending through at least a portion of a thickness of and along a perimeter, where the first and second microelectronic components are coupled by direct bonding; and a seal ring formed by coupling the first guard ring to the second guard ring. In some embodiments, a microelectronic assembly may include a microelectronic component coupled to an interposer that includes a first liner material at a first surface; a second liner material at an opposing second surface; and a perimeter wall through the interposer and connected to the first and second liner materials.