公开(公告)号：US20240063132A1

公开(公告)日：2024-02-22

申请号：US17820993

申请日：2022-08-19

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Scott E. Siers ,  Gerald S. Pasdast ,  Johanna M. Swan ,  Henning Braunisch ,  Kimin Jun ,  Jiraporn Seangatith ,  Shawna M. Liff ,  Mohammad Enamul Kabir ,  Sathya Narasimman Tiagaraj

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/5386 ,  H01L24/08 ,  H01L24/16 ,  H01L24/80 ,  H01L24/05 ,  H01L25/0652 ,  H01L25/0657 ,  H01L23/5383 ,  H01L2224/05647 ,  H01L2224/05687 ,  H01L2224/16225 ,  H01L2224/08145 ,  H01L2224/08121 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2924/37001 ,  H01L2924/3841 ,  H01L2924/3512

Abstract: Embodiments of a microelectronic assembly comprise: a plurality of layers of IC dies, adjacent layers in the plurality of layers being coupled together by first interconnects and a package substrate coupled to the plurality of layers by second interconnects. A first layer in the plurality of layers comprises a dielectric material surrounding a first IC die in the first layer, a second layer in the plurality of layers is adjacent and non-coplanar with the first layer, the second layer comprises a first circuit region and a second circuit region separated by a third circuit region, the first circuit region and the second circuit region are bounded by respective guard rings, and the first IC die comprises conductive pathways conductively coupling conductive traces in the first circuit region with conductive traces in the second circuit region.

公开(公告)号：US20220399277A1

公开(公告)日：2022-12-15

申请号：US17345969

申请日：2021-06-11

Applicant: INTEL CORPORATION

Inventor： Adel A. Elsherbini ,  Scott E. Siers ,  Sathya Narasimman Tiagaraj ,  Gerald S. Pasdast ,  Zhiguo Qian ,  Kalyan C. Kolluru ,  Vivek Kumar Rajan ,  Shawna M. Liff ,  Johanna M. Swan

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H01L21/48 ,  H01L25/00

Abstract: An Integrated Circuit (IC), comprising a first conductive trace on a first die, a second conductive trace on a second die, and a conductive pathway electrically coupling the first conductive trace with the second conductive trace. The second die is coupled to the first die with interconnects. The conductive pathway comprises a portion of the interconnects located proximate to a periphery of a region in the first die through which the first conductive trace is not routable. In some embodiments, the conductive pathway reroutes electrical connections away from the region. The region comprises a high congestion zone having high routing density in some embodiments. In other embodiments, the region comprises a “keep-out” zone.