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    TWO-TERMINAL INTEGRATED CIRCUIT DEVICE FOR ELECTROSTATIC DISCHARGE PROTECTION
    1.
    发明申请
    TWO-TERMINAL INTEGRATED CIRCUIT DEVICE FOR ELECTROSTATIC DISCHARGE PROTECTION 有权

    公开(公告)号：US20240413147A1

    公开(公告)日：2024-12-12

    申请号：US18332918

    申请日：2023-06-12

    Applicant: Intel Corporation

    Inventor： Ayan Kar ,  Kalyan C. Kolluru

    IPC: H01L27/02

    Abstract: A two-terminal IC device may be used for ESD protection. The IC device may include a deep N-well may be between a P-type substrate and a group of wells that includes a first P-well, a second P-well, and a N-well. There may be another well between the second P-well and the N-well. A P-type semiconductor structure may be formed in the P-well. Two N-type semiconductor structures may be formed in the second P-well and the N-well, respectively. A contact of the P-type semiconductor structure may be electrically coupled to a contact of the N-type semiconductor structure in the second P-well. The two contacts may constitute the first terminal of the IC device. The contact of the N-type semiconductor structure in the N-well may constitute the second terminal of the IC device. The first P-well may have a greater dimension but lower dopant concentration than the second P-well or the N-well.

    INTEGRATED CIRCUIT STRUCTURES INCLUDING BACKSIDE VIAS
    3.
    发明申请
    INTEGRATED CIRCUIT STRUCTURES INCLUDING BACKSIDE VIAS 有权

    公开(公告)号：US20210202472A1

    公开(公告)日：2021-07-01

    申请号：US16728111

    申请日：2019-12-27

    Applicant: Intel Corporation

    Inventor： Nicholas A. Thomson ,  Kalyan C. Kolluru ,  Adam Clay Faust ,  Frank Patrick O'Mahony ,  Ayan Kar ,  Rui Ma

    IPC: H01L27/02

    Abstract: Disclosed herein are integrated circuit (IC) structures including backside vias, as well as related methods and devices. In some embodiments, an IC structure may include: a device layer, wherein the device layer includes a plurality of active devices; a first metallization layer over the device layer, wherein the first metallization layer includes a first conductive pathway in conductive contact with at least one of the active devices in the device layer; a second metallization layer under the device layer, wherein the second metallization layer includes a second conductive pathway; and a conductive via in the device layer, wherein the conductive via is in conductive contact with at least one of the active devices in the device layer and also in conductive contact with the second conductive pathway.

    VERTICAL DIODES IN STACKED TRANSISTOR TECHNOLOGIES
    5.
    发明申请
    VERTICAL DIODES IN STACKED TRANSISTOR TECHNOLOGIES 有权

    公开(公告)号：US20230089395A1

    公开(公告)日：2023-03-23

    申请号：US17448373

    申请日：2021-09-22

    Applicant: INTEL CORPORATION

    Inventor： Benjamin Orr ,  Nicholas A. Thomson ,  Ayan Kar ,  Nathan D. Jack ,  Kalyan C. Kolluru ,  Patrick Morrow ,  Cheng-Ying Huang ,  Charles C. Kuo

    IPC: H01L27/06 ,  H01L27/092 ,  H01L29/66 ,  H01L21/8238

    Abstract: Integrated circuits including vertical diodes. In an example, a first transistor is above a second transistor. The first transistor includes a first semiconductor body extending laterally from a first source or drain region. The first source or drain region includes one of a p-type dopant or an n-type dopant. The second transistor includes a second semiconductor body extending laterally from a second source or drain region. The second source or drain region includes the other of the p-type dopant or the n-type dopant. The first source or drain region and second source or drain region are at least part of a diode structure, which may have a PN junction (e.g., first and second source/drain regions are merged) or a PIN junction (e.g., first and second source/drain regions are separated by an intrinsic semiconductor layer, or a dielectric layer and the first and second semiconductor bodies are part of the junction).

    Integrated circuit structures including backside vias
    7.
    发明授权
    Integrated circuit structures including backside vias 有权

    公开(公告)号：US12294003B2

    公开(公告)日：2025-05-06

    申请号：US18457453

    申请日：2023-08-29

    Applicant: Intel Corporation

    Inventor： Nicholas A. Thomson ,  Kalyan C. Kolluru ,  Adam Clay Faust ,  Frank Patrick O'Mahony ,  Ayan Kar ,  Rui Ma

    IPC: H01L21/677 ,  H01L27/02

    Abstract: Disclosed herein are integrated circuit (IC) structures including backside vias, as well as related methods and devices. In some embodiments, an IC structure may include: a device layer, wherein the device layer includes a plurality of active devices; a first metallization layer over the device layer, wherein the first metallization layer includes a first conductive pathway in conductive contact with at least one of the active devices in the device layer; a second metallization layer under the device layer, wherein the second metallization layer includes a second conductive pathway; and a conductive via in the device layer, wherein the conductive via is in conductive contact with at least one of the active devices in the device layer and also in conductive contact with the second conductive pathway.

    TRANSISTOR DEVICES WITH EXTENDED DRAIN
    8.
    发明公开
    TRANSISTOR DEVICES WITH EXTENDED DRAIN 审中-公开

    公开(公告)号：US20240088136A1

    公开(公告)日：2024-03-14

    申请号：US17943557

    申请日：2022-09-13

    Applicant: Intel Corporation

    Inventor： Ayan Kar ,  Nicholas A. Thomson ,  Kalyan C. Kolluru ,  Benjamin Orr

    IPC: H01L27/02

    CPC classification number: H01L27/027

    Abstract: An integrated circuit structure includes a sub-fin, a source region in contact with a first portion of the sub-fin, and a drain region in contact with a second portion of the sub-fin. A body including semiconductor material is above the sub-fin, where the body extends laterally between the source region and the drain region. A gate structure is on the body and includes (i) a gate electrode, and (ii) a gate dielectric between the gate electrode and the body. In an example, a first distance between the drain region and the gate electrode is at least two times a second distance between the source region and the gate electrode, where the first and second distances are measured in a same horizontal plane that runs in a direction parallel to the body. In an example, the body is a nanoribbon, a nanosheet, a nanowire, or a fin.

    VARACTOR DEVICE WITH BACKSIDE ELECTRICAL CONTACT
    9.
    发明公开
    VARACTOR DEVICE WITH BACKSIDE ELECTRICAL CONTACT 审中-公开

    公开(公告)号：US20230420578A1

    公开(公告)日：2023-12-28

    申请号：US17848660

    申请日：2022-06-24

    Applicant: Intel Corporation

    Inventor： Ayan Kar ,  Kalyan C. Kolluru ,  Nicholas A. Thomson ,  Vijaya Bhaskara Neeli ,  Said Rami ,  Saurabh Morarka ,  Karthik Krishaswamy ,  Mauro J. Kobrinsky

    IPC: H01L29/93 ,  H01L29/06 ,  H01L29/417

    CPC classification number: H01L29/93 ,  H01L29/0673 ,  H01L29/417 ,  H01L29/42392

    Abstract: A varactor device includes a support structure, an electrically conductive layer at the backside of the support structure, two semiconductor structures including doped semiconductor materials, two contact structures, and a semiconductor region. Each contract structure is electrically conductive and is connected to a different one of the semiconductor structures A contract structure couples the corresponding semiconductor structure to the electrically conductive layer. The semiconductor region is between the two semiconductor structures and can be connected to the two semiconductor structures. The semiconductor region may include non-planar semiconductor structures coupled with a gate. The gate may be coupled to another electrically conductive layer at the frontside of the support structure. The varactor device may further include a pair of additional semiconductor regions that are electrically insulated from each other. The additional semiconductor regions may be coupled to two oppositely polarized gates, respectively.

    INTEGRATED CIRCUIT STRUCTURES INCLUDING BACKSIDE VIAS
    10.
    发明公开
    INTEGRATED CIRCUIT STRUCTURES INCLUDING BACKSIDE VIAS 审中-公开

    公开(公告)号：US20230402449A1

    公开(公告)日：2023-12-14

    申请号：US18457453

    申请日：2023-08-29

    Applicant: Intel Corporation

    Inventor： Nicholas A. Thomson ,  Kalyan C. Kolluru ,  Adam Clay Faust ,  Frank Patrick O'Mahony ,  Ayan Kar ,  Rui Ma

    IPC: H01L27/02

    CPC classification number: H01L27/0292 ,  H01L27/0288 ,  H01L27/0255

    Abstract: Disclosed herein are integrated circuit (IC) structures including backside vias, as well as related methods and devices. In some embodiments, an IC structure may include: a device layer, wherein the device layer includes a plurality of active devices; a first metallization layer over the device layer, wherein the first metallization layer includes a first conductive pathway in conductive contact with at least one of the active devices in the device layer; a second metallization layer under the device layer, wherein the second metallization layer includes a second conductive pathway; and a conductive via in the device layer, wherein the conductive via is in conductive contact with at least one of the active devices in the device layer and also in conductive contact with the second conductive pathway.

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