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    PHY-BASED RETRY TECHNIQUES FOR DIE-TO-DIE INTERFACES
    3.
    发明申请
    PHY-BASED RETRY TECHNIQUES FOR DIE-TO-DIE INTERFACES 有权

    公开(公告)号：US20210344354A1

    公开(公告)日：2021-11-04

    申请号：US17359517

    申请日：2021-06-26

    Applicant: Intel Corporation

    Inventor： Narasimha Lanka ,  Lakshmipriya Seshan ,  Debendra Das Sharma ,  Zuoguo Wu ,  Gerald S. Pasdast

    IPC: H03M13/11 ,  H03M13/00

    Abstract: In one embodiment, an apparatus includes PHY circuitry to implement a PHY-based retry technique, e.g., in die-to-die interfaces. The PHY circuitry includes a retry buffer to buffer data provided by the interface controller and error detection code generation circuitry to generate error detection codes based on input data. The PHY circuitry is to implement the retry technique by detecting a stall signal asserted by another apparatus across the channel, causing the error detection code generation circuitry to generate error detection codes based on data in the retry buffer, and transmitting the data from the retry buffer and its corresponding error detection codes across the channel to the other apparatus.

    FAST-LANE ROUTING FOR MULTI-CHIP PACKAGES
    5.
    发明申请
    FAST-LANE ROUTING FOR MULTI-CHIP PACKAGES 审中-公开

    公开(公告)号：US20200067816A1

    公开(公告)日：2020-02-27

    申请号：US16106926

    申请日：2018-08-21

    Applicant: Intel Corporation

    Inventor： Adel A. Elsherbini ,  Tejpal Singh ,  Shawna M. Liff ,  Gerald S. Pasdast ,  Johanna M. Swan

    IPC: H04L12/733 ,  H04L12/933 ,  G06F12/0842 ,  H04L29/06

    Abstract: Embodiments herein may relate to a processor package with a substrate and a multi-chip processor coupled with the substrate. The multi-chip processor may include a dual-sided interconnect structure coupled with a first chip, a second chip, and a third chip. The first chip may be communicatively coupled with the second chip by an on-chip communication route. Likewise, the second chip may be communicatively coupled with the first chip by an on-chip communication route. Additionally, the first chip may be communicatively coupled with the third chip by a fast-lane communication route. Other embodiments may be described and/or claimed.

    Method, apparatus, system for centering in a high performance interconnect
    9.
    发明授权
    Method, apparatus, system for centering in a high performance interconnect 有权

    公开(公告)号：US10560081B2

    公开(公告)日：2020-02-11

    申请号：US15632836

    申请日：2017-06-26

    Applicant: Intel Corporation

    Inventor： Mahesh Wagh ,  Zuoguo J. Wu ,  Venkatraman Iyer ,  Gerald S. Pasdast ,  Todd A. Hinck ,  David M. Lee ,  Narasimha R. Lanka

    IPC: H03K5/26 ,  G01R31/04 ,  H03L9/00 ,  G06F1/3296 ,  G06F13/42 ,  H03K5/131

    Abstract: In an example, a system and method for centering in a high-performance interconnect (HPI) are disclosed. When an interconnect is powered up from a dormant state, it may be necessary to “center” the clock signal to ensure that data are read at the correct time. A multi-phase method may be used, in which a first phase comprises a reference voltage sweep to identify an optimal reference voltage. A second phase comprises a phase sweep to identify an optimal phase. A third sweep comprises a two-dimensional “eye” phase, in which a plurality of values within a two-dimensional eye derived from the first two sweeps are tested. In each case, the optimal value is the value that results in the fewest bit error across multiple lanes. In one example, the second and third phases are performed in software, and may include testing a “victim” lane, with adjacent “aggressor” lanes having a complementary bit pattern.

    VALID LANE TRAINING
    10.
    发明申请
    VALID LANE TRAINING 审中-公开

    公开(公告)号：US20190238179A1

    公开(公告)日：2019-08-01

    申请号：US15761408

    申请日：2015-09-26

    Applicant: Intel Corporation

    Inventor： Venkatraman Iyer ,  Lip Khoon Teh ,  Mahesh Wagh ,  Zuoguo Wu ,  Azydee Hamid ,  Gerald S. Pasdast

    IPC: H04B3/40 ,  H04L25/03 ,  G06F13/20

    CPC classification number: H04B3/40 ,  G06F13/20 ,  G06F13/40 ,  H04L25/03006 ,  H04L2025/0377

    Abstract: One or more link training signals are received, including instances of a link training pattern, on a plurality of lanes of a physical link that includes at least one valid lane and a plurality of data lanes. The plurality of lanes are trained together using the link training signals to synchronize sampling of the valid lane with sampling of the plurality of data lanes. An active link state is entered and a valid signal received on the valid lane during the active link state. The valid signal includes a signal held at a value for a defined first duration and indicates that data is to be received on the plurality of data lanes in a second defined duration subsequent to the first duration. The data is to be received, during the active link state, on the plurality of data lanes during the second defined duration.

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