公开(公告)号：US20130328168A1

公开(公告)日：2013-12-12

申请号：US13737467

申请日：2013-01-09

Applicant: INTERMOLECULAR INC.

Inventor： Sandra G. Malhotra ,  Wim Y. Deweerd ,  Hiroyuki Ode

IPC: H01L49/02

CPC classification number: H01L28/56 ,  H01L27/10852 ,  H01L28/60 ,  H01L28/90

Abstract: A method for forming a capacitor stack is described. In some embodiments of the present invention, a first dielectric material is formed above a first electrode material. The first electrode material is rigid and has good mechanical strength and serves as a robust frame for the capacitor stack. The first dielectric material is sufficiently thin ( 3nm) or lightly doped or non-doped so that it crystallizes after subsequent anneal treatments. A second electrode material is formed adjacent to the second dielectric material. The second electrode material has a high work function and a crystal structure that serves to promote the formation of the high k-value crystal structure of the second dielectric material.

Abstract translation: 描述形成电容器堆叠的方法。 在本发明的一些实施例中，第一电介质材料形成在第一电极材料之上。 第一电极材料是刚性的并且具有良好的机械强度并且用作用于电容器叠层的坚固框架。 第一介电材料足够薄（<2nm）或高度掺杂，使得在随后的退火处理之后它保持非晶态。 在第一电介质材料上方形成第二电介质材料。 第二介电材料足够厚（> 3nm）或轻掺杂或未掺杂，使得其在随后的退火处理之后结晶。 与第二电介质材料相邻地形成第二电极材料。 第二电极材料具有高功函数和用于促进形成第二电介质材料的高k值晶体结构的晶体结构。

公开(公告)号：US20130217202A1

公开(公告)日：2013-08-22

申请号：US13830282

申请日：2013-03-14

Applicant: Intermolecular, Inc. ,  Elpida Memory, Inc.

Inventor： Sandra G. Malhotra ,  Hanhong Chen ,  Wim Y. Deweerd ,  Mitsuhiro Horikawa ,  Kenichi Koyanagi ,  Hiroyuki Ode ,  Xiangxin Rui

IPC: H01L49/02

CPC classification number: H01L28/60 ,  H01L28/40 ,  H01L28/75

Abstract: A method for fabricating a DRAM capacitor stack is described wherein the dielectric material is a multi-layer stack formed from a highly-doped material combined with a lightly or non-doped material. The highly-doped material remains amorphous with a crystalline content of less than 30% after an annealing step. The lightly or non-doped material becomes crystalline with a crystalline content of equal to or greater than 30% after an annealing step. The dielectric multi-layer stack maintains a high k-value while minimizing the leakage current and the EOT value.

公开(公告)号：US20130056851A1

公开(公告)日：2013-03-07

申请号：US13664922

申请日：2012-10-31

Applicant: Intermolecular, Inc. ,  Elpida Memory, Inc.

Inventor： Hanhong Chen ,  Wim Y. Deweerd ,  Hiroyuki Ode

IPC: H01B5/00 ,  H01L29/92

CPC classification number: H01L28/65 ,  H01L28/75

Abstract: A metal oxide bilayer second electrode for a MIM DRAM capacitor is formed wherein the layer of the electrode that is in contact with the dielectric layer (i.e. bottom layer) has a desired composition and crystal structure. An example is crystalline MoO2 if the dielectric layer is TiO2 in the rutile phase. The other component of the bilayer (i.e. top layer) is a sub-oxide of the same material as the bottom layer. The top layer serves to protect the bottom layer from oxidation during subsequent PMA or other DRAM fabrication steps by reacting with any oxygen species before they can reach the bottom layer of the bilayer second electrode.

Abstract translation: 形成用于MIM DRAM电容器的金属氧化物双层第二电极，其中与电介质层（即，底层）接触的电极层具有期望的组成和晶体结构。 如果电介质层是金红石相中的TiO 2，那么结晶MoO2就是一个例子。 双层的另一部分（即顶层）是与底层相同的材料的次氧化物。 顶层用于在随后的PMA或其它DRAM制造步骤期间通过与任何氧物种反应而在它们可以到达双层第二电极的底层之前保护底层免受氧化。

公开(公告)号：US08975633B2

公开(公告)日：2015-03-10

申请号：US13664922

申请日：2012-10-31

Applicant: Intermolecular, Inc. ,  Elpida Memory, Inc.

Inventor： Hanhong Chen ,  Wim Y. Deweerd ,  Hiroyuki Ode

IPC: H01L27/108 ,  H01L29/00 ,  H01L29/12 ,  H01L29/786 ,  H01L49/02

CPC classification number: H01L28/65 ,  H01L28/75

Abstract: A metal oxide bilayer second electrode for a MIM DRAM capacitor is formed wherein the layer of the electrode that is in contact with the dielectric layer (i.e. bottom layer) has a desired composition and crystal structure. An example is crystalline MoO2 if the dielectric layer is TiO2 in the rutile phase. The other component of the bilayer (i.e. top layer) is a sub-oxide of the same material as the bottom layer. The top layer serves to protect the bottom layer from oxidation during subsequent PMA or other DRAM fabrication steps by reacting with any oxygen species before they can reach the bottom layer of the bilayer second electrode.

Abstract translation: 形成用于MIM DRAM电容器的金属氧化物双层第二电极，其中与电介质层（即，底层）接触的电极层具有期望的组成和晶体结构。 如果电介质层是金红石相中的TiO 2，那么结晶MoO2就是一个例子。 双层的另一部分（即顶层）是与底层相同的材料的次氧化物。 顶层用于在随后的PMA或其它DRAM制造步骤期间通过与任何氧物种反应而在它们可以到达双层第二电极的底层之前保护底层免受氧化。

公开(公告)号：US08652927B2

公开(公告)日：2014-02-18

申请号：US13738510

申请日：2013-01-10

Applicant: Intermolecular, Inc.

Inventor： Sandra Malhotra ,  Hanhong Chen ,  Wim Y. Deweerd ,  Edward L. Haywood ,  Hiroyuki Ode ,  Gerald Richardson

IPC: H01L21/20

CPC classification number: H01L29/92 ,  H01L28/75 ,  H01L28/92

Abstract: A method for forming a capacitor stack is described. In some embodiments of the present invention, a first electrode structure is comprised of multiple materials. A first material is formed above the substrate. A portion of the first material is etched. A second material is formed above the first material. A portion of the second material is etched. Optionally, the first electrode structure receives an anneal treatment. A dielectric material is formed above the first electrode structure. Optionally, the dielectric material receives an anneal treatment. A second electrode material is formed above the dielectric material. Typically, the capacitor stack receives an anneal treatment.

Abstract translation: 描述形成电容器堆叠的方法。 在本发明的一些实施例中，第一电极结构由多种材料构成。 在基板上方形成第一材料。 蚀刻第一材料的一部分。 在第一材料上方形成第二材料。 蚀刻第二材料的一部分。 可选地，第一电极结构接受退火处理。 介电材料形成在第一电极结构之上。 可选地，电介质材料接受退火处理。 在电介质材料上方形成第二电极材料。 通常，电容器堆叠接收退火处理。

公开(公告)号：US20130320495A1

公开(公告)日：2013-12-05

申请号：US13738510

申请日：2013-01-10

Applicant: INTERMOLECULAR, INC.

Inventor： Sandra G. Malhotra ,  Hanhong Chen ,  Wim Y. Deweerd ,  Edward L. Haywood ,  Hiroyuki Ode ,  Gerald Richardson

IPC: H01L29/92

CPC classification number: H01L29/92 ,  H01L28/75 ,  H01L28/92

Abstract: A method for forming a capacitor stack is described. In some embodiments of the present invention, a first electrode structure is comprised of multiple materials. A first material is formed above the substrate. A portion of the first material is etched. A second material is formed above the first material. A portion of the second material is etched. Optionally, the first electrode structure receives an anneal treatment. A dielectric material is formed above the first electrode structure. Optionally, the dielectric material receives an anneal treatment. A second electrode material is formed above the dielectric material. Typically, the capacitor stack receives an anneal treatment.

Abstract translation: 描述形成电容器堆叠的方法。 在本发明的一些实施例中，第一电极结构由多种材料构成。 在基板上方形成第一材料。 蚀刻第一材料的一部分。 在第一材料上方形成第二材料。 蚀刻第二材料的一部分。 可选地，第一电极结构接受退火处理。 介电材料形成在第一电极结构之上。 可选地，电介质材料接受退火处理。 在电介质材料上方形成第二电极材料。 通常，电容器堆叠接收退火处理。

公开(公告)号：US08542523B2

公开(公告)日：2013-09-24

申请号：US13738855

申请日：2013-01-10

Applicant: Intermolecular Inc.

Inventor： Karthik Ramani ,  Wim Y. Deweerd ,  Hiroyuki Ode

IPC: G11C11/00

CPC classification number: H01L28/65 ,  H01L28/20 ,  H01L45/06 ,  H01L45/1206 ,  H01L45/122 ,  H01L45/1286 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1683 ,  Y10S977/754

Abstract: A method for fabricating a dynamic random access memory (DRAM) capacitor includes forming a first electrode film. The first electrode film comprises a conductive binary metal compound and a dopant. The dopant may have a uniform or non-uniform concentration within the first electrode film. A high-k dielectric film is formed over the first electrode film. A second electrode film is formed over the dielectric film. The second electrode film comprises a conductive binary metal compound and a dopant. The dopant may have a uniform or non-uniform concentration within the second electrode film. The dopants and their distribution are chosen so that the crystal structure of the surface of the electrode is not degraded if the electrode is to be used as a templating structure for subsequent layer formation. Additionally, the dopants and their distribution are chosen so that the work function of the electrodes is not degraded.

公开(公告)号：US20130209927A1

公开(公告)日：2013-08-15

申请号：US13827969

申请日：2013-03-14

Applicant: INTERMOLECULAR INC.

Inventor： Wim Y. Deweerd

IPC: G03F1/52

CPC classification number: G03F1/52 ,  G03F1/22 ,  G03F1/24

Abstract: A photomask is provide. The photomask includes a substrate having a multi-layer stack disposed over the substrate. The multilayer stack has alternating first second and third layers disposed over each other, wherein the first, second and third layers are composed of first, second and third materials, respectively, and wherein at least the second layer is formed through an atomic layer deposition process. A capping layer is disposed over the multilayer stack; and an absorber layer disposed over the capping layer. A method for evaluating materials, unit processes, and process sequences for manufacturing a photomask is also provided.

公开(公告)号：US20130122683A1

公开(公告)日：2013-05-16

申请号：US13738865

申请日：2013-01-10

Applicant: Intermolecular Inc. ,  Elpida Memory, Inc

Inventor： Sandra G. Malhotra ,  Hanhong Chen ,  Wim Y. Deweerd ,  Hiroyuki Ode

IPC: H01L49/02

CPC classification number: H01L28/60 ,  H01L27/10852 ,  H01L28/40

Abstract: A method for forming a DRAM MIM capacitor stack having low leakage current involves the use of a first electrode that serves as a template for promoting the high k phase of a subsequently deposited dielectric layer. The high k dielectric layer comprises a doped material that can be crystallized after a subsequent annealing treatment. An amorphous blocking is formed on the dielectric layer. The thickness of the blocking layer is chosen such that the blocking layer remains amorphous after a subsequent annealing treatment. A second electrode layer compatible with the blocking layer is formed on the blocking layer.

Abstract translation: 用于形成具有低泄漏电流的DRAM MIM电容器堆叠的方法涉及使用用作促进随后沉积的介电层的高k相的模板的第一电极。 高k电介质层包括可在随后的退火处理后结晶的掺杂材料。 在电介质层上形成无定形阻挡层。 选择阻挡层的厚度使得在随后的退火处理之后阻挡层保持无定形。 在阻挡层上形成与阻挡层相容的第二电极层。

公开(公告)号：US20130119515A1

公开(公告)日：2013-05-16

申请号：US13738855

申请日：2013-01-10

Applicant: Intermolecular Inc.

Inventor： Karthik Ramani ,  Wim Y. Deweerd ,  Hiroyuki Ode

IPC: H01L49/02

CPC classification number: H01L28/65 ,  H01L28/20 ,  H01L45/06 ,  H01L45/1206 ,  H01L45/122 ,  H01L45/1286 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1683 ,  Y10S977/754

Abstract: A method for fabricating a dynamic random access memory (DRAM) capacitor includes forming a first electrode film. The first electrode film comprises a conductive binary metal compound and a dopant. The dopant may have a uniform or non-uniform concentration within the first electrode film. A high-k dielectric film is formed over the first electrode film. A second electrode film is formed over the dielectric film. The second electrode film comprises a conductive binary metal compound and a dopant. The dopant may have a uniform or non-uniform concentration within the second electrode film. The dopants and their distribution are chosen so that the crystal structure of the surface of the electrode is not degraded if the electrode is to be used as a templating structure for subsequent layer formation. Additionally, the dopants and their distribution are chosen so that the work function of the electrodes is not degraded.

Abstract translation: 一种用于制造动态随机存取存储器（DRAM）电容器的方法包括形成第一电极膜。 第一电极膜包括导电二元金属化合物和掺杂剂。 掺杂剂可以在第一电极膜内具有均匀或不均匀的浓度。 在第一电极膜上形成高k电介质膜。 在绝缘膜上形成第二电极膜。 第二电极膜包括导电二元金属化合物和掺杂剂。 掺杂剂可以在第二电极膜内具有均匀或不均匀的浓度。 选择掺杂剂及其分布，使得如果将电极用作后续层形成的模板结构，则电极表面的晶体结构不会降解。 此外，选择掺杂剂及其分布使得电极的功函数不降解。