公开(公告)号：US20200105628A1

公开(公告)日：2020-04-02

申请号：US16145143

申请日：2018-09-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Yann Mignot ,  Alan Thomas ,  Daniel Sanders ,  Dario Goldfarb ,  Nelson Felix ,  Chi-Chun Liu ,  John Arnold

IPC: H01L21/66 ,  H01L21/02 ,  H01L21/311

Abstract: An exemplary semiconductor wafer includes a lower sublayer of a first organic planarization layer (OPL) material; an upper sublayer of a second OPL material deposited onto the lower sublayer; and a detectable interface between the lower sublayer and the upper sublayer. The exemplary wafer is fabricated by depositing the lower sublayer; curing the lower sublayer; and after curing the lower sublayer, depositing the upper sublayer directly onto the lower sublayer.

公开(公告)号：US11830807B2

公开(公告)日：2023-11-28

申请号：US17499123

申请日：2021-10-12

Applicant: International Business Machines Corporation

Inventor： Ashim Dutta ,  Ekmini Anuja De Silva ,  Dominik Metzler ,  John Arnold

IPC: H01L23/522 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/76816 ,  H01L21/76879 ,  H01L21/76897 ,  H01L23/5283

Abstract: Embodiments of the present invention are directed to fabrication method and resulting structures for placing self-aligned top vias at line ends of an interconnect structure. In a non-limiting embodiment of the invention, a line feature is formed in a metallization layer of an interconnect structure. The line feature can include a line hard mask. A trench is formed in the line feature to expose line ends of the line feature. The trench is filled with a host material and a growth inhibitor is formed over a first line end of the line feature. A via mask is formed over a second line end of the line feature. The via mask can be selectively grown on an exposed surface of the host material. Portions of the line feature that are not covered by the via mask are recessed to define a self-aligned top via at the second line end.

公开(公告)号：US20220028784A1

公开(公告)日：2022-01-27

申请号：US17499123

申请日：2021-10-12

Applicant: International Business Machines Corporation

Inventor： Ashim DUTTA ,  Ekmini Anuja De Silva ,  Dominik METZLER ,  John Arnold

IPC: H01L23/522 ,  H01L23/528 ,  H01L21/768

Abstract: Embodiments of the present invention are directed to fabrication method and resulting structures for placing self-aligned top vias at line ends of an interconnect structure. In a non-limiting embodiment of the invention, a line feature is formed in a metallization layer of an interconnect structure. The line feature can include a line hard mask. A trench is formed in the line feature to expose line ends of the line feature. The trench is filled with a host material and a growth inhibitor is formed over a first line end of the line feature. A via mask is formed over a second line end of the line feature. The via mask can be selectively grown on an exposed surface of the host material. Portions of the line feature that are not covered by the via mask are recessed to define a self-aligned top via at the second line end.

公开(公告)号：US11189561B2

公开(公告)日：2021-11-30

申请号：US16574447

申请日：2019-09-18

Applicant: International Business Machines Corporation

Inventor： Ashim Dutta ,  Ekmini Anuja De Silva ,  Dominik Metzler ,  John Arnold

IPC: H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768

Abstract: Embodiments of the present invention are directed to fabrication method and resulting structures for placing self-aligned top vias at line ends of an interconnect structure. In a non-limiting embodiment of the invention, a line feature is formed in a metallization layer of an interconnect structure. The line feature can include a line hard mask. A trench is formed in the line feature to expose line ends of the line feature. The trench is filled with a host material and a growth inhibitor is formed over a first line end of the line feature. A via mask is formed over a second line end of the line feature. The via mask can be selectively grown on an exposed surface of the host material. Portions of the line feature that are not covered by the via mask are recessed to define a self-aligned top via at the second line end.

公开(公告)号：US11158786B2

公开(公告)日：2021-10-26

申请号：US16582762

申请日：2019-09-25

Applicant: International Business Machines Corporation

Inventor： Ashim Dutta ,  Chih-Chao Yang ,  Lijuan Zou ,  John Arnold

IPC: H01L43/12 ,  H01L43/10 ,  H01L43/02 ,  H01L27/22

Abstract: Controlled IBE techniques for MRAM stack patterning are provided. In one aspect, a method of forming an MRAM device includes: patterning an MRAM stack disposed on a dielectric into individual memory cells using IBE landing on the dielectric while dynamically adjusting an etch time to compensate for variations in a thickness of the MRAM stack, wherein each of the memory cells includes a bottom electrode, an MTJ, and a top electrode; removing foot flares from the bottom electrode of the memory cells which are created during the patterning of the MRAM stack; removing residue from sidewalls of the memory cells which includes metal redeposited during the patterning of the MRAM stack and during the removing of the foot flares; and covering the memory cells in a dielectric encapsulant. An MRAM device is also provided.

公开(公告)号：US11152261B2

公开(公告)日：2021-10-19

申请号：US16664830

申请日：2019-10-26

Applicant: International Business Machines Corporation

Inventor： Ashim Dutta ,  John Arnold ,  Dominik Metzler

IPC: H01L21/768 ,  H01L21/033 ,  H01L23/522 ,  H01L23/532

Abstract: Techniques for self-aligned top via formation at line ends are provided. In one aspect, a method of forming self-aligned vias at line ends includes: patterning (even/odd) metal lines including using a (first/second) hardmask; cutting the hardmask and a select metal line, even or odd, using a cut mask having a window that exposes the hardmask over a cut region of the select metal line; enlarging the window to expose the hardmask on either side of the cut region; selectively etching the hardmask using the enlarged window to form a T-shaped cavity within the cut region; filling the T-shaped cavity with a gap fill dielectric; removing the hardmask; and recessing the metal lines, wherein the gap fill dielectric overhangs portions of the select metal line that, by the recessing, form the self-aligned vias at ends of the metal lines. A structure is also provided.