公开(公告)号：US10896976B2

公开(公告)日：2021-01-19

申请号：US16541437

申请日：2019-08-15

Applicant: International Business Machines Corporation

Inventor： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Ali Khakifirooz ,  Henry K. Utomo ,  Reinaldo Ariel Vega

IPC: H01L21/8234 ,  H01L29/78 ,  H01L29/04 ,  H01L29/66 ,  H01L29/06 ,  H01L21/762 ,  H01L29/16 ,  H01L21/02 ,  H01L29/08 ,  H01L21/84 ,  H01L29/417 ,  H01L27/088 ,  H01L29/165

Abstract: A shallow trench isolation layer is formed on a structure comprising semiconductor fins. Portions of the fins are recessed to a level below the shallow trench isolation layer. Epitaxial stressor regions are then formed on the recessed fin areas. A bottom portion of the epitaxial stressor regions are contained by the shallow trench isolation layer, which delays formation of the diamond shape as the epitaxial region is grown. Once the epitaxial stressor regions exceed the level of the shallow trench isolation layer, the diamond shape starts to form. The result of delaying the start of the diamond growth pattern is that the epitaxial regions are narrower for a given fin height. This allows for taller fins, which provide more current handling capacity, while the narrower epitaxial stressor regions enable a smaller fin pitch, allowing for increased circuit density.

公开(公告)号：US20200350403A1

公开(公告)日：2020-11-05

申请号：US16401226

申请日：2019-05-02

Applicant: International Business Machines Corporation

Inventor： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Theodorus E. Standaert ,  Junli Wang

IPC: H01L29/08 ,  H01L29/10 ,  H01L29/78 ,  H01L29/417 ,  H01L29/66 ,  H01L21/306 ,  H01L29/45 ,  H01L29/40

Abstract: An integrated semiconductor device having a substrate, a bottom source or drain (S/D) structure formed on the substrate. In addition, the device includes a fin extending from the bottom S/D structure and a gate formed around the fin. A top S/D structure is formed on top of the fin. The top S/D structure includes a recessed top S/D surface and a silicide layer covering a top portion of the recess. A contact is communicatively coupled to a surface of the silicide layer of the recessed top S/D surface of the top S/D structure.

公开(公告)号：US10784365B2

公开(公告)日：2020-09-22

申请号：US16264955

申请日：2019-02-01

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Veeraraghavan S. Basker ,  Zuoguang Liu ,  Tenko Yamashita ,  Chun-Chen Yeh

IPC: H01L29/66 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L29/40 ,  H01L21/311 ,  H01L21/62 ,  H01L21/3213 ,  H01L21/8234 ,  H01L21/3065 ,  H01L21/265 ,  H01L21/02 ,  H01L29/08 ,  H01L27/088

Abstract: A method of forming a fin field effect transistor (finFET), including forming a temporary gate structure having a sacrificial gate layer and a dummy gate layer on the sacrificial gate layer, forming a gate spacer layer on each sidewall of the temporary gate structure, forming a source/drain spacer layer on the outward-facing sidewall of each gate spacer layer, removing the dummy gate layer to expose the sacrificial gate layer, removing the sacrificial gate layer to form a plurality of recessed cavities, and forming a gate structure, where the gate structure occupies at least a portion of the plurality of recessed cavities.

公开(公告)号：US10692989B2

公开(公告)日：2020-06-23

申请号：US16568780

申请日：2019-09-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Theodorus E. Standaert ,  Junli Wang

IPC: H01L21/311 ,  H01L29/66 ,  H01L21/768 ,  H01L29/49 ,  H01L23/485 ,  H01L29/417 ,  H01L23/532 ,  H01L23/535 ,  H01L29/78 ,  H01L29/51

Abstract: Replacement metal gate structures with improved chamfered workfunction metal and self-aligned contact and methods of manufacture are provided. The method includes forming a replacement metal gate structure in a dielectric material. The replacement metal gate structure is formed with a lower spacer and an upper spacer above the lower spacer. The upper spacer having material is different than material of the lower spacer. The method further includes forming a self-aligned contact adjacent to the replacement metal gate structure by patterning an opening within the dielectric material and filling the opening with contact material. The upper spacer prevents shorting with the contact material.

公开(公告)号：US10672887B2

公开(公告)日：2020-06-02

申请号：US15838890

申请日：2017-12-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Junli Wang ,  Kangguo Cheng ,  Theodorus E. Standaert ,  Veeraraghavan S. Basker

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/78

Abstract: A vertical transistor includes a first source/drain region and a second source/drain region vertically disposed relative to the first source/drain region and coupled to the first source/drain region by a fin. A gate dielectric is formed on the fin, and a gate conductor is formed on the gate dielectric in a region of the fin. A shaped spacer is configured to cover a lower portion and sides of the second source/drain region to reduce parasitic capacitance between the gate conductor and the second source/drain region.

公开(公告)号：US10658224B2

公开(公告)日：2020-05-19

申请号：US16126621

申请日：2018-09-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Huimei Zhou ,  Gen Tsutsui ,  Veeraraghavan S. Basker ,  Andrew M. Greene ,  Dechao Guo ,  Huiming Bu ,  Reinaldo Vega

IPC: H01L27/088 ,  H01L21/762 ,  H01L21/02 ,  H01L21/306 ,  H01L29/66 ,  H01L29/78 ,  H01L21/32

Abstract: Integrated chips and methods of forming the same include oxidizing a portion of a semiconductor fin, which includes a channel layer and an intermediate semiconductor layer, to electrically isolate active regions of the semiconductor fin by forming an oxide that fully penetrates the channel layer and the intermediate semiconductor layer. A semiconductor device is formed on each of the active regions.

公开(公告)号：US20200152751A1

公开(公告)日：2020-05-14

申请号：US16687736

申请日：2019-11-19

Applicant: International Business Machines Corporation

Inventor： Andrew Greene ,  Dechao Guo ,  Tenko Yamashita ,  Veeraraghavan S. Basker ,  Robert Robison ,  Ardasheir Rahman

IPC: H01L29/417 ,  H01L29/40 ,  H01L21/8234 ,  H01L21/285

Abstract: A technique relates to a semiconductor device. A source or drain (S/D) contact liner is formed on one or more S/D regions. Annealing is performed to form a silicide layer around the one or more S/D regions, the silicide layer being formed at an interface between the S/D contact liner and the S/D regions. A block layer is formed into a pattern over the one or more S/D regions, such that a portion of the S/D contact liner is protected by the block layer. Unprotected portions of the S/D contact liner are removed, such that the S/D contact liner protected by the block layer remains over the one or more S/D regions. The block layer and S/D contacts are formed on the S/D contact liner over the one or more S/D regions.

公开(公告)号：US10651295B2

公开(公告)日：2020-05-12

申请号：US16269607

申请日：2019-02-07

Applicant: International Business Machines Corporation

Inventor： Veeraraghavan S. Basker ,  Pouya Hashemi ,  Shogo Mochizuki ,  Alexander Reznicek

IPC: H01L29/66 ,  H01L29/417 ,  H01L29/20 ,  H01L29/78 ,  H01L21/84 ,  H01L29/267 ,  H01L29/40 ,  H01L21/762 ,  H01L29/06

Abstract: The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming a fin using double trench epitaxy. The fin may be composed of a III-V semiconductor material and may be grown on a silicon, silicon germanium, or germanium substrate. A double trench aspect ratio trapping (ART) epitaxy method may trap crystalline defects within a first trench (i.e. a defective region) and may permit formation of a fin free of patterning defects in an upper trench (i.e. a fin mold). Crystalline defects within the defective region may be trapped via conventional aspect ratio trapping or three-sided aspect ratio trapping. Fin patterning defects may be avoided by utilizing a fin mold to grow an epitaxial fin and selectively removing dielectric material adjacent to a fin region.

公开(公告)号：US10593622B2

公开(公告)日：2020-03-17

申请号：US16132922

申请日：2018-09-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Ali Khakifirooz ,  Juntao Li

IPC: H01L23/525 ,  H01L23/522 ,  H01L23/532 ,  H01L49/02 ,  H01L23/535 ,  H01L27/06 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/8234 ,  H01C17/00 ,  H01H69/02 ,  H01L29/49 ,  H01L29/66

Abstract: Electrical fuse (eFuse) and resistor structures and methods of manufacture are provided. The method includes forming metal gates having a capping material on a top surface thereof. The method further includes protecting the metal gates and the capping material during an etching process which forms a recess in a dielectric material. The method further includes forming an insulator material and metal material within the recess. The method further includes forming a contact in direct electrical contact with the metal material.

公开(公告)号：US10586867B2

公开(公告)日：2020-03-10

申请号：US15864269

申请日：2018-01-08

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Veeraraghavan S. Basker ,  Theodorus E. Standaert ,  Junli Wang

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10

Abstract: A semiconductor structure, such as a strained FinFETs, includes a strain relief buffer (SRB) layer isolated and separated from a source and a drain by a spacer that may be simultaneously formed with a gate spacer upon the sidewalls of a gate structure. The spacer limits the source and drain from contacting the SRB layer thereby limiting source drain junction leakage. Further, the spacer limits source and drain punch through to the SRB layer underneath a channel. An etch may partially remove a SRB layer portion within a fin stack. The etch undercuts the source and drain forming a fin void without under cutting the channel. The spacer may be formed by depositing spacer material with the fin void.