公开(公告)号：US20080081406A1

公开(公告)日：2008-04-03

申请号：US11750491

申请日：2007-05-18

申请人： Jae-ouk Choo ,  II-young Yoon ,  Seo-woo Nam ,  Ja-eung Koo

发明人： Jae-ouk Choo ,  II-young Yoon ,  Seo-woo Nam ,  Ja-eung Koo

IPC分类号： H01L29/739

CPC分类号： H01L21/823425 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/7843

摘要： A method of fabricating a semiconductor device comprising providing a substrate including a PMOS region and an NMOS region forming a PMOS gate electrode on the PMOS region and an NMOS gate electrode on the NMOS gate region, respectively, forming a stress liner on the PMOS region formed with the PMOS gate on the PMOS region and the NMOS region formed with the NMOS gate electrode on the NMOS region, and selectively applying radiation onto the stress liner formed on either one of the PMOS region and the NMOS region in an inert vapor ambiance.

摘要翻译： 一种制造半导体器件的方法，包括在PMOS区上提供包括PMOS区和PMOS栅电极的NMOS区和在NMOS栅区上的NMOS栅电极的衬底，所述衬底在形成的PMOS区上形成应力衬垫 PMOS晶体管上的PMOS栅极和NMOS区域上形成有NMOS栅电极的NMOS区域，并以惰性蒸气气氛，选择性地将辐射施加到形成在PMOS区域和NMOS区域中的任一个上的应力衬垫上。

公开(公告)号：US20100065919A1

公开(公告)日：2010-03-18

申请号：US12621079

申请日：2009-11-18

申请人： Seo-woo Nam ,  Ki-chul Kim ,  Young-joon Moon ,  Jae-ouk Choo ,  Hong-jae Shin ,  Nae-in Lee

发明人： Seo-woo Nam ,  Ki-chul Kim ,  Young-joon Moon ,  Jae-ouk Choo ,  Hong-jae Shin ,  Nae-in Lee

IPC分类号： H01L27/092

CPC分类号： H01L21/823412 ,  H01L21/823807 ,  H01L27/088 ,  H01L27/092 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor substrate includes a first transistor area having a first gate electrode and first source/drain areas, a second transistor area having a second gate electrode and second source/drain areas, and an interface area provided at an interface of the first transistor area and the second transistor area and having a third gate electrode. A first stress film is on the first gate electrode and the first source/drain areas of the first transistor area and at least a portion of the third gate electrode of the interface area. A second stress film is on the second gate electrode and the second source/drain areas of the second transistor area and not overlapping the first stress film on the third gate electrode of the interface area or overlapping at least a portion of the first stress film. The second stress film overlapping at least the portion of the first stress film is thinner than the second stress film in the second transistor area. Related methods are also described.

摘要翻译： 半导体衬底包括具有第一栅极电极和第一源极/漏极区域的第一晶体管区域，具有第二栅极电极和第二源极/漏极区域的第二晶体管区域，以及设置在第一晶体管区域和 第二晶体管区域并具有第三栅电极。 第一应力膜位于第一栅极电极和第一晶体管区域的第一源极/漏极区域和界面区域的第三栅极电极的至少一部分之间。 第二应力膜位于第二晶体管区域的第二栅极电极和第二源极/漏极区域上，并且不与界面区域的第三栅电极上的第一应力膜重叠或与第一应力膜的至少一部分重叠。 与第一应力膜的至少部分重叠的第二应力膜比第二晶体管区域中的第二应力膜更薄。 还描述了相关方法。

公开(公告)号：US07642148B2

公开(公告)日：2010-01-05

申请号：US11851500

申请日：2007-09-07

申请人： Seo-woo Nam ,  Ki-chul Kim ,  Young-joon Moon ,  Jae-ouk Choo ,  Hong-jae Shin ,  Nae-in Lee

发明人： Seo-woo Nam ,  Ki-chul Kim ,  Young-joon Moon ,  Jae-ouk Choo ,  Hong-jae Shin ,  Nae-in Lee

IPC分类号： H01L21/8238

CPC分类号： H01L21/823412 ,  H01L21/823807 ,  H01L27/088 ,  H01L27/092 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor substrate includes a first transistor area having a first gate electrode and first source/drain areas, a second transistor area having a second gate electrode and second source/drain areas, and an interface area provided at an interface of the first transistor area and the second transistor area and having a third gate electrode. A first stress film is on the first gate electrode and the first source/drain areas of the first transistor area and at least a portion of the third gate electrode of the interface area. A second stress film is on the second gate electrode and the second source/drain areas of the second transistor area and not overlapping the first stress film on the third gate electrode of the interface area or overlapping at least a portion of the first stress film. The second stress film overlapping at least the portion of the first stress film is thinner than the second stress film in the second transistor area. Related methods are also described.

摘要翻译： 半导体衬底包括具有第一栅极电极和第一源极/漏极区域的第一晶体管区域，具有第二栅极电极和第二源极/漏极区域的第二晶体管区域，以及设置在第一晶体管区域和 第二晶体管区域并具有第三栅电极。 第一应力膜位于第一栅极电极和第一晶体管区域的第一源极/漏极区域和界面区域的第三栅极电极的至少一部分之间。 第二应力膜位于第二晶体管区域的第二栅极电极和第二源极/漏极区域上，并且不与界面区域的第三栅电极上的第一应力膜重叠或与第一应力膜的至少一部分重叠。 与第一应力膜的至少部分重叠的第二应力膜比第二晶体管区域中的第二应力膜更薄。 还描述了相关方法。

公开(公告)号：US20090280637A1

公开(公告)日：2009-11-12

申请号：US12453326

申请日：2009-05-07

申请人： Kyoung-woo Lee ,  Hong-jae Shin ,  Jae-hak Kim ,  Jae-ouk Choo

发明人： Kyoung-woo Lee ,  Hong-jae Shin ,  Jae-hak Kim ,  Jae-ouk Choo

IPC分类号： H01L21/768

CPC分类号： H01L21/7682 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02271 ,  H01L21/02282 ,  H01L21/02304 ,  H01L21/02348 ,  H01L21/02351 ,  H01L21/02362 ,  H01L21/31695

摘要： Provided is a method of manufacturing a semiconductor device. The method employs multi-step removal on a plurality of different porogens included in a low dielectric layer both before and after metal lines are formed, thereby facilitating formation of an ultra low dielectric constant layer which is used as an insulation layer between metal lines of a semiconductor device. The method may include forming an interlayer dielectric layer on a substrate, forming a plurality of porogens in the interlayer dielectric layer, removing a portion of the plurality of porogens in the interlayer dielectric layer to form a plurality of first pores in the interlayer dielectric layer, forming a wiring pattern where the plurality of first pores are formed, and removing the remaining porogens of the plurality of porogens to form a plurality of second pores in the interlayer dielectric layer.

摘要翻译： 提供一种制造半导体器件的方法。 该方法在形成金属线之前和之后，在包含在低电介质层中的多个不同的致孔剂上采用多步除去，从而有助于形成超低介电常数层，该超低介电常数层用作金属线之间的绝缘层 半导体器件。 该方法可以包括在衬底上形成层间电介质层，在层间电介质层中形成多个致孔剂，去除层间电介质层中的多个致孔剂的一部分，以在层间电介质层中形成多个第一孔， 形成其中形成有多个第一孔的布线图案，并且除去多个致孔剂中剩余的孔隙原，以在层间电介质层中形成多个第二孔。

公开(公告)号：US20080079087A1

公开(公告)日：2008-04-03

申请号：US11851500

申请日：2007-09-07

申请人： Seo-woo Nam ,  Ki-chul Kim ,  Young-joon Moon ,  Jae-ouk Choo ,  Hong-jae Shin ,  Nae-in Lee

发明人： Seo-woo Nam ,  Ki-chul Kim ,  Young-joon Moon ,  Jae-ouk Choo ,  Hong-jae Shin ,  Nae-in Lee

IPC分类号： H01L29/78 ,  H01L21/8238

CPC分类号： H01L21/823412 ,  H01L21/823807 ,  H01L27/088 ,  H01L27/092 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor substrate includes a first transistor area having a first gate electrode and first source/drain areas, a second transistor area having a second gate electrode and second source/drain areas, and an interface area provided at an interface of the first transistor area and the second transistor area and having a third gate electrode. A first stress film is on the first gate electrode and the first source/drain areas of the first transistor area and at least a portion of the third gate electrode of the interface area. A second stress film is on the second gate electrode and the second source/drain areas of the second transistor area and not overlapping the first stress film on the third gate electrode of the interface area or overlapping at least a portion of the first stress film. The second stress film overlapping at least the portion of the first stress film is thinner than the second stress film in the second transistor area. Related methods are also described.

摘要翻译： 半导体衬底包括具有第一栅极电极和第一源极/漏极区域的第一晶体管区域，具有第二栅极电极和第二源极/漏极区域的第二晶体管区域，以及设置在第一晶体管区域和 第二晶体管区域并具有第三栅电极。 第一应力膜位于第一栅极电极和第一晶体管区域的第一源极/漏极区域和界面区域的第三栅极电极的至少一部分之间。 第二应力膜位于第二晶体管区域的第二栅极电极和第二源极/漏极区域上，并且不与界面区域的第三栅电极上的第一应力膜重叠或与第一应力膜的至少一部分重叠。 与第一应力膜的至少部分重叠的第二应力膜比第二晶体管区域中的第二应力膜更薄。 还描述了相关方法。