公开(公告)号：US10156535B2

公开(公告)日：2018-12-18

申请号：US14961906

申请日：2015-12-08

Applicant: Industrial Technology Research Institute

Inventor： Sih-Han Li ,  Chih-Sheng Lin ,  Kuan-Wei Chen ,  Erh-Hao Chen ,  Shyh-Shyuan Sheu

IPC: G01N27/12

Abstract: A sensor device and a method of manufacturing the same are provided. The sensor device includes a substrate, a plurality of sensing electrodes, a humidity nanowire sensor, a temperature nanowire sensor, and a gas nanowire sensor. The sensing electrodes are formed on the substrate, and the humidity, the temperature and the gas nanowire sensors are also on the substrate. The humidity nanowire sensor includes an exposed first nanowire sensing region, the temperature nanowire sensor includes a second nanowire sensing region, and the gas nanowire sensor includes a third nanowire sensing region.

公开(公告)号：US20170115248A1

公开(公告)日：2017-04-27

申请号：US14958856

申请日：2015-12-03

Applicant: Industrial Technology Research Institute

Inventor： Chih-Sheng Lin ,  Erh-Hao Chen ,  Sih-Han Li ,  Kuan-Wei Chen ,  Shyh-Shyuan Sheu

IPC: G01N27/12

CPC classification number: G01N27/127

Abstract: A gas sensing apparatus including a gas sensor, a gas determining circuit and a gas database is provided. The gas sensor includes at least two nanowire sensors. The gas sensor is configured to sense multiple gases and output a plurality of sensing signals. The gas determining circuit is coupled to the gas sensor. The gas determining circuit is configured to receive the sensing signals and determine types of the gases according to reference data and the sensing signals. The gas database is coupled to the gas determining circuit. The gas database stores the reference data and outputs the reference data to the gas determining circuit. Each of the nanowire sensors includes at least one nanowire. Structural properties of the nanowires are different.

公开(公告)号：US20140175606A1

公开(公告)日：2014-06-26

申请号：US13974909

申请日：2013-08-23

Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

Inventor： Sih-Han Li ,  Pei-Ling Tseng ,  Zhe-Hui Lin ,  Chih-Sheng Lin

IPC: H01L49/02

CPC classification number: H01L23/481 ,  H01L27/0808 ,  H01L29/93 ,  H01L29/94 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A varactor is provided. A substrate includes a first surface, a second surface and a first opening and a second opening in the substrate. A conductive material is filling the first and second openings, to form a first through-wafer via (TWV) and a second through-wafer via. A first capacitor is coupled between the first through-wafer via and a first terminal. A second capacitor is coupled between the second through-wafer via and a second terminal. A capacitance of a depletion-region capacitor between the first through-wafer via and the second through-wafer via is determined by a bias voltage applied to the first through-wafer via and the second through-wafer via.

Abstract translation: 提供变容二极管。 衬底包括衬底中的第一表面，第二表面和第一开口以及第二开口。 导电材料填充第一和第二开口，以形成第一贯穿晶片通孔（TWV）和第二通晶片通孔。 第一电容器耦合在第一通晶片通孔和第一端子之间。 第二电容器耦合在第二通晶片通孔和第二端子之间。 第一贯穿晶片通孔和第二贯通晶片通孔之间的耗尽区电容器的电容由施加到第一贯穿晶片通孔和第二贯通晶片通孔的偏置电压决定。

公开(公告)号：US20250103751A1

公开(公告)日：2025-03-27

申请号：US18896914

申请日：2024-09-26

Applicant: Industrial Technology Research Institute

Inventor： Bo-Cheng Chiou ,  Chih-Sheng Lin ,  Tuo-Hung Hou ,  Chih-Ming Lai ,  Yun-Ting Ho ,  Shan-Ming Chang

IPC: G06F21/62 ,  G06F21/72 ,  H04L9/32

Abstract: A computing circuit with a de-identified architecture, a data computing method, a data processing system, and a data de-identification method are provided. The computing circuit includes an arithmetic array and a de-identification circuit. The computing circuit may perform an accumulation operation on input data to generate accumulated data by the arithmetic array. The de-identification circuit has an analog offset error determined based on an analog physical unclonable function. The computing circuit may operate the accumulated data according to the analog offset error to generate de-identification data by the de-identification circuit. It can not only provide the analog offset error through the transistors in the de-identification circuit, but also be combined with obfuscated code settings to dynamically adjusting the degree of de-identification of data.

公开(公告)号：US20230267973A1

公开(公告)日：2023-08-24

申请号：US18074528

申请日：2022-12-05

Applicant: Industrial Technology Research Institute

Inventor： Chih-Sheng Lin ,  Fu-Cheng Tsai ,  Tuo-Hung Hou ,  Jian-Wei Su ,  Yu-Hui Lin ,  Chih-Ming Lai

IPC: G11C7/06 ,  G11C7/12 ,  G11C7/10

CPC classification number: G11C7/067 ,  G11C7/12 ,  G11C7/1063

Abstract: According to an exemplary embodiments, the disclosure is directed to a memory circuit which includes not limited to a first half sense amplifier circuit connected to a first plurality of memory cells through a first bit line and configured to receive a unit of analog electrical signal from each of the first plurality of memory cells and to generate a first half sense amplifier output signal corresponding to the first bit line based on a first gain of the half sense amplifier and an accumulation of the units of analog signals, a locking code register circuit configured to receive a locking data and to generate a digital locking sequence, and a source selector circuit configured to receive the digital locking sequence and to generate a first adjustment signal to adjust the first half sense amplifier output signal corresponding to the first bit line by adjusting the first gain.

公开(公告)号：US20230153375A1

公开(公告)日：2023-05-18

申请号：US18155762

申请日：2023-01-18

Applicant: Industrial Technology Research Institute

Inventor： Chih-Sheng Lin ,  Jian-Wei Su ,  Tuo-Hung Hou ,  Sih-Han Li ,  Fu-Cheng Tsai ,  Yu-Hui Lin

IPC: G06F17/16 ,  G11C11/412

CPC classification number: G06F17/16 ,  G11C11/412

Abstract: A computing in memory (CIM) cell includes a memory cell circuit, a first semiconductor element, a second semiconductor element, a third semiconductor element, and a fourth semiconductor element. A first terminal of the first semiconductor element receives a bias voltage. A control terminal of the first semiconductor element is coupled to a computing word-line. A control terminal of the second semiconductor element is coupled to a first data node in the memory cell circuit. A second terminal of the third semiconductor element is adapted to receive a reference voltage. A control terminal of the third semiconductor element receives an inverted signal of the computing word-line. A first terminal of the fourth semiconductor element is coupled to a first computing bit-line. A second terminal of the fourth semiconductor element is coupled to a second computing bit-line.

公开(公告)号：US20220413801A1

公开(公告)日：2022-12-29

申请号：US17679090

申请日：2022-02-24

Applicant: Industrial Technology Research Institute

Inventor： Jian-Wei Su ,  Chih-Sheng Lin ,  Peng-I Mei ,  Sih-Han Li ,  Shyh-Shyuan Sheu ,  Jheng Yang Dai

IPC: G06F7/523 ,  G06F7/50

Abstract: A configurable computing unit within memory including a first input transistor, a first weight transistor, a first resistor, a second input transistor, a second weight transistor, and a second resistor is provided. The first input transistor, the first weight transistor, and the first resistor are coupled in series between a first readout bit line and a common signal line. The first input transistor is coupled to a first input bit line, and the first weight transistor receives a first weight bit. The second input transistor, the second weight transistor, and the second resistor are coupled in series between the first readout bit line and the common signal line. The second input transistor is coupled to a second input bit line, and the second weight transistor receives the second weight bit.

公开(公告)号：US20190079039A1

公开(公告)日：2019-03-14

申请号：US16178599

申请日：2018-11-02

Applicant: Industrial Technology Research Institute

Inventor： Sih-Han Li ,  Chih-Sheng Lin ,  Kuan-Wei Chen ,  Erh-Hao Chen ,  Shyh-Shyuan Sheu

IPC: G01N27/12

Abstract: A method of manufacturing a sensor device is provided. In the method, sensing electrodes are formed on a substrate, a sensing material layer is formed on the sensing electrodes. The sensing material layer is etched to form a first nanowire sensing region, a second nanowire sensing region and a third nanowire sensing region respectively between every two sensing electrodes of the sensing electrodes. A dielectric layer is formed to cover the first nanowire sensing region, the second nanowire sensing region and the third nanowire sensing region, and the first nanowire sensing region and the third nanowire sensing region are exposed.

公开(公告)号：US20180238822A1

公开(公告)日：2018-08-23

申请号：US15955691

申请日：2018-04-18

Applicant: Industrial Technology Research Institute

Inventor： Kuan-Wei Chen ,  Chih-Sheng Lin ,  Erh-Hao Chen ,  Sih-Han Li ,  Shyh-Shyuan Sheu

IPC: G01N27/12

CPC classification number: G01N27/127 ,  G01N27/122 ,  G01N33/0031

Abstract: A gas sensing apparatus including a gas sensor, a gas determining circuit and a gas database is provided. The gas sensor includes at least two nanowire sensors. The gas sensor is configured to sense multiple gases and output a plurality of sensing signals. The gas determining circuit is coupled to the gas sensor. The gas determining circuit is configured to receive the sensing signals and determine types of the gases according to reference data and the sensing signals. The gas database is coupled to the gas determining circuit. The gas database stores the reference data and outputs the reference data to the gas determining circuit. Each of the nanowire sensors includes at least one nanowire. Structural properties of the nanowires are different.

公开(公告)号：US09076771B2

公开(公告)日：2015-07-07

申请号：US13974909

申请日：2013-08-23

Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

Inventor： Sih-Han Li ,  Pei-Ling Tseng ,  Zhe-Hui Lin ,  Chih-Sheng Lin

IPC: H01L29/93 ,  H01L23/48 ,  H01L27/08 ,  H01L29/94

CPC classification number: H01L23/481 ,  H01L27/0808 ,  H01L29/93 ,  H01L29/94 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A varactor is provided. A substrate includes a first surface, a second surface and a first opening and a second opening in the substrate. A conductive material is filling the first and second openings, to form a first through-wafer via (TWV) and a second through-wafer via. A first capacitor is coupled between the first through-wafer via and a first terminal. A second capacitor is coupled between the second through-wafer via and a second terminal. A capacitance of a depletion-region capacitor between the first through-wafer via and the second through-wafer via is determined by a bias voltage applied to the first through-wafer via and the second through-wafer via.

Abstract translation: 提供变容二极管。 衬底包括衬底中的第一表面，第二表面和第一开口以及第二开口。 导电材料填充第一和第二开口，以形成第一贯穿晶片通孔（TWV）和第二通晶片通孔。 第一电容器耦合在第一通晶片通孔和第一端子之间。 第二电容器耦合在第二通晶片通孔和第二端子之间。 第一贯穿晶片通孔和第二贯通晶片通孔之间的耗尽区电容器的电容由施加到第一贯穿晶片通孔和第二贯通晶片通孔的偏置电压决定。