公开(公告)号：US10510626B2

公开(公告)日：2019-12-17

申请号：US15377371

申请日：2016-12-13

Applicant: Infineon Technologies AG

Inventor： Michaela Braun ,  Markus Menath

IPC: H01L21/66 ,  H01L21/78 ,  H01L21/683 ,  H01L21/3065

Abstract: In one embodiment, a wafer includes a number of die areas each including a semiconductor device and dedicated to become a separate die. The die areas are disposed on a first face of the wafer and wherein adjacent die areas are distanced from one another. A first trench and a second trench are formed on the first face between adjacent die areas. The first trench and the second trench are spaced apart from one another by a ridge. A third trench is disposed above the ridge on a second face of the wafer.

公开(公告)号：US09780161B2

公开(公告)日：2017-10-03

申请号：US14837880

申请日：2015-08-27

Applicant: Infineon Technologies AG

Inventor： Markus Menath ,  Thomas Fischer ,  Hermann Wendt

IPC: H01F17/02 ,  H01F38/14 ,  H01L23/522 ,  H01L23/64 ,  H01L49/02 ,  H01F17/00 ,  H01F41/04 ,  H01L23/528 ,  H01L27/08 ,  H01L21/768 ,  H01L21/50 ,  H01L21/02 ,  H01L21/027

CPC classification number: H01L28/10 ,  H01F17/0006 ,  H01F17/02 ,  H01F41/042 ,  H01L21/0274 ,  H01L21/76804 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5227 ,  H01L23/5283 ,  H01L23/64 ,  H01L27/08 ,  H01L2224/48095 ,  H01L2224/48137 ,  Y10T29/4902 ,  H01L2924/00014

Abstract: A method for manufacturing an electronic device and an electronic device are disclosed. In an embodiment the method comprises forming an opening in an isolation layer, isotropically etching the opening thereby forming an extended opening with curved sidewalls, and forming a conductive material in the opening.

公开(公告)号：US20170092552A1

公开(公告)日：2017-03-30

申请号：US15377371

申请日：2016-12-13

Applicant: Infineon Technologies AG

Inventor： Michaela Braun ,  Markus Menath

IPC: H01L21/66 ,  H01L21/683 ,  H01L21/3065 ,  H01L21/78

Abstract: In one embodiment, a wafer includes a number of die areas each including a semiconductor device and dedicated to become a separate die. The die areas are disposed on a first face of the wafer and wherein adjacent die areas are distanced from one another. A first trench and a second trench are formed on the first face between adjacent die areas. The first trench and the second trench are spaced apart from one another by a ridge. A third trench is disposed above the ridge on a second face of the wafer.

公开(公告)号：US20170084468A1

公开(公告)日：2017-03-23

申请号：US15365971

申请日：2016-12-01

Applicant: Infineon Technologies AG

Inventor： Markus Menath

IPC: H01L21/56 ,  H01L21/78 ,  H01L21/3065 ,  H01L23/544

CPC classification number: H01L21/561 ,  H01L21/30655 ,  H01L21/3086 ,  H01L21/78 ,  H01L23/544 ,  H01L2223/5446

Abstract: In various embodiments, a method for processing a wafer may include: providing a wafer having at least one die region and at least one metallization disposed over the at least one die region; covering the at least one metallization with a protecting layer; plasma etching the wafer to form at least one die.

公开(公告)号：US20160311679A1

公开(公告)日：2016-10-27

申请号：US15138313

申请日：2016-04-26

Applicant: Infineon Technologies AG

Inventor： Dominic Maier ,  Alfons Dehe ,  Thomas Kilger ,  Markus Menath ,  Franz Xaver Muehlbauer ,  Daniel Porwol ,  Juergen Wagner

IPC: B81C1/00 ,  B81B7/00

CPC classification number: B81C1/00896 ,  B81C1/00269 ,  B81C1/00801 ,  B81C2201/0194 ,  B81C2201/053

Abstract: A method of producing a chip package is described. A plurality of chips is provided on a first wafer. Each chip has a cavity which opens to a first main face of the chip. The cavities are filled or covered temporarily. The chips are then singulated. The singulated chips are embedded in an encapsulation material, and then the cavities are re-exposed.

Abstract translation: 对芯片封装的制造方法进行说明。 多个芯片设置在第一晶片上。 每个芯片具有通向芯片的第一主面的空腔。 空腔被暂时填充或覆盖。 然后将芯片分开。 单片化芯片嵌入封装材料中，然后将空腔重新曝光。