公开(公告)号：US11282805B2

公开(公告)日：2022-03-22

申请号：US16360570

申请日：2019-03-21

Applicant: Infineon Technologies AG

Inventor： Michael Roesner ,  Markus Menath ,  Gudrun Stranzl

IPC: H01L29/45 ,  H01L23/00 ,  H01L21/04 ,  H01L29/16

Abstract: A semiconductor device includes a silicon carbide layer, a metal carbide layer arranged over the silicon carbide layer, and a solder layer arranged over and in contact with the metal carbide layer.

公开(公告)号：US09981843B2

公开(公告)日：2018-05-29

申请号：US15138313

申请日：2016-04-26

Applicant: Infineon Technologies AG

Inventor： Dominic Maier ,  Alfons Dehe ,  Thomas Kilger ,  Markus Menath ,  Franz Xaver Muehlbauer ,  Daniel Porwol ,  Juergen Wagner

IPC: H01L29/84 ,  B81C1/00

CPC classification number: B81C1/00896 ,  B81C1/00269 ,  B81C1/00801 ,  B81C2201/0194 ,  B81C2201/053

Abstract: A method of producing a chip package is described. A plurality of chips is provided on a first wafer. Each chip has a cavity which opens to a first main face of the chip. The cavities are filled or covered temporarily. The chips are then singulated. The singulated chips are embedded in an encapsulation material, and then the cavities are re-exposed.

公开(公告)号：US09553022B1

公开(公告)日：2017-01-24

申请号：US14792419

申请日：2015-07-06

Applicant: Infineon Technologies AG

Inventor： Michaela Braun ,  Markus Menath

IPC: H01L21/00 ,  H01L21/78 ,  H01L21/66 ,  H01L23/31 ,  H01L21/683 ,  H01L21/3065

CPC classification number: H01L22/30 ,  H01L21/3065 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L22/34 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381

Abstract: In one embodiment, a wafer includes a number of die areas each including a semiconductor device and dedicated to become a separate die. The die areas are disposed on a first face of the wafer and wherein adjacent die areas are distanced from one another. A first trench and a second trench are formed on the first face between adjacent die areas. The first trench and the second trench are spaced apart from one another by a ridge. A third trench is disposed above the ridge on a second face of the wafer.

Abstract translation: 在一个实施例中，晶片包括多个管芯区域，每个管芯区域包括半导体器件，并专用于成为单独的管芯。 管芯区域设置在晶片的第一面上，并且其中相邻的管芯区域彼此间隔开。 第一沟槽和第二沟槽形成在相邻裸片区域之间的第一面上。 第一沟槽和第二沟槽通过脊彼此间隔开。 第三沟槽设置在晶片的第二面上的脊上方。

公开(公告)号：US20170011963A1

公开(公告)日：2017-01-12

申请号：US14792419

申请日：2015-07-06

Applicant: Infineon Technologies AG

Inventor： Michaela Braun ,  Markus Menath

IPC: H01L21/78 ,  H01L21/3065 ,  H01L21/683 ,  H01L21/66 ,  H01L23/31

CPC classification number: H01L22/30 ,  H01L21/3065 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L22/34 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381

Abstract: In one embodiment, a wafer includes a number of die areas each including a semiconductor device and dedicated to become a separate die. The die areas are disposed on a first face of the wafer and wherein adjacent die areas are distanced from one another. A first trench and a second trench are formed on the first face between adjacent die areas. The first trench and the second trench are spaced apart from one another by a ridge. A third trench is disposed above the ridge on a second face of the wafer.

Abstract translation: 在一个实施例中，晶片包括多个管芯区域，每个管芯区域包括半导体器件，并专用于成为单独的管芯。 管芯区域设置在晶片的第一面上，并且其中相邻的管芯区域彼此间隔开。 第一沟槽和第二沟槽形成在相邻裸片区域之间的第一面上。 第一沟槽和第二沟槽通过脊彼此间隔开。 第三沟槽设置在晶片的第二面上的脊上方。

公开(公告)号：US20150372073A1

公开(公告)日：2015-12-24

申请号：US14837880

申请日：2015-08-27

Applicant: Infineon Technologies AG

Inventor： Markus Menath ,  Thomas Fischer ,  Hermann Wendt

IPC: H01L49/02

CPC classification number: H01L28/10 ,  H01F17/0006 ,  H01F17/02 ,  H01F41/042 ,  H01L21/0274 ,  H01L21/76804 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5227 ,  H01L23/5283 ,  H01L23/64 ,  H01L27/08 ,  H01L2224/48095 ,  H01L2224/48137 ,  Y10T29/4902 ,  H01L2924/00014

Abstract: A method for manufacturing an electronic device and an electronic device are disclosed. In an embodiment the method comprises forming an opening in an isolation layer, isotropically etching the opening thereby forming an extended opening with curved sidewalls, and forming a conductive material in the opening.

Abstract translation: 公开了一种电子设备和电子设备的制造方法。 在一个实施例中，该方法包括在隔离层中形成开口，各向同性地蚀刻开口，从而形成具有弯曲侧壁的延伸开口，并在开口中形成导电材料。

公开(公告)号：US20190308274A1

公开(公告)日：2019-10-10

申请号：US16374265

申请日：2019-04-03

Applicant: Infineon Technologies AG

Inventor： Michael Roesner ,  Markus Menath ,  Gudrun Stranzl

IPC: B23K26/362 ,  B23K26/40 ,  H01L21/67 ,  H01L21/3065 ,  H01L29/16

Abstract: A method of processing silicon carbide containing crystalline substrate is provided. The method includes pyrolyzing a surface of the silicon carbide containing crystalline substrate to produce a silicon and carbon containing debris layer over the silicon carbide containing crystalline substrate, and removing the silicon and carbon containing debris layer, wherein the pyrolyzing and the removing is repeated at least once.

公开(公告)号：US20190295981A1

公开(公告)日：2019-09-26

申请号：US16360570

申请日：2019-03-21

Applicant: Infineon Technologies AG

Inventor： Michael Roesner ,  Markus Menath ,  Gudrun Stranzl

IPC: H01L23/00 ,  H01L29/16 ,  H01L29/45 ,  H01L21/04

Abstract: A semiconductor device includes a silicon carbide layer, a metal carbide layer arranged over the silicon carbide layer, and a solder layer arranged over and in contact with the metal carbide layer.

公开(公告)号：US09576875B2

公开(公告)日：2017-02-21

申请号：US14591014

申请日：2015-01-07

Applicant: Infineon Technologies AG

Inventor： Reinhard Hess ,  Katharina Umminger ,  Gabriel Maier ,  Markus Menath ,  Gunther Mackh ,  Hannes Eder ,  Alexander Heinrich

IPC: H01L23/31 ,  H01L23/485 ,  H01L21/78 ,  H01L21/3065 ,  H01L21/56 ,  H01L23/00 ,  H01L21/683 ,  H01L21/02 ,  H01L21/768

CPC classification number: H01L23/3171 ,  H01L21/02107 ,  H01L21/30655 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/3185 ,  H01L23/485 ,  H01L24/05 ,  H01L2224/0236 ,  H01L2224/02372 ,  H01L2224/02375 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/05548 ,  H01L2224/0556 ,  H01L2224/0557 ,  H01L2224/05611 ,  H01L2224/05618 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/0566 ,  H01L2224/05664 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/01029 ,  H01L2924/01013 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01046 ,  H01L2924/0103 ,  H01L2924/01028 ,  H01L2924/01026 ,  H01L2224/05552

Abstract: A method for manufacturing a chip arrangement is provided, the method including: forming a hole in a carrier including at least one chip, wherein forming a hole in the carrier includes: selectively removing carrier material, thereby forming a cavity in the carrier, forming passivation material over one or more cavity walls exposed by the selective removal of the carrier material; selectively removing a portion of the passivation material and further carrier material exposed by the selective removal of the passivation material, wherein a further portion of the passivation material remains over at least one cavity side wall; the method further including subsequently forming a layer over the further portion of passivation material remaining over the at least one cavity side wall.

Abstract translation: 提供了一种制造芯片布置的方法，该方法包括：在载体中形成一个孔，该载体包括至少一个芯片，其中在载体中形成孔包括：选择性地去除载体材料，从而在载体中形成空腔，形成钝化 通过选择性去除载体材料暴露的一个或多个腔壁上的材料; 选择性地去除钝化材料的一部分和通过选择性去除钝化材料暴露的另外的载体材料，其中钝化材料的另一部分保留在至少一个空腔侧壁上; 该方法还包括随后在保留在至少一个空腔侧壁上的钝化材料的另一部分上形成层。

公开(公告)号：US20150380306A1

公开(公告)日：2015-12-31

申请号：US14320402

申请日：2014-06-30

Applicant: Infineon Technologies AG

Inventor： Markus Menath

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/528 ,  H01L21/311 ,  H01L21/3213

CPC classification number: H01L23/5226 ,  H01L21/32115 ,  H01L21/7684 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming a vertical electrical conductive connection includes forming an electrically insulating layer including at least one hole reaching vertically through the electrically insulating layer and depositing an electrically conductive layer. A surface of the electrically conductive layer includes a recess at the location of the at least one hole of the electrically insulating layer. Further, the method includes forming a smoothing layer on the electrically conductive layer and etching the smoothing layer and the electrically conductive layer until the electrically conductive layer is removed above at least a part of a surface of the electrically insulating layer and remains within the at least one hole.

Abstract translation: 形成垂直导电连接的方法包括形成电绝缘层，该电绝缘层包括至少一个垂直穿过电绝缘层的孔，并沉积导电层。 导电层的表面包括在电绝缘层的至少一个孔的位置处的凹部。 此外，该方法包括在导电层上形成平滑层并蚀刻平滑层和导电层，直到导电层在电绝缘层的至少一部分表面上除去并保持在至少 一个洞。

公开(公告)号：US11077525B2

公开(公告)日：2021-08-03

申请号：US16374265

申请日：2019-04-03

Applicant: Infineon Technologies AG

Inventor： Michael Roesner ,  Markus Menath ,  Gudrun Stranzl

IPC: B23K26/362 ,  B23K26/40 ,  H01L29/16 ,  H01L21/3065 ,  H01L21/67

Abstract: A method of processing silicon carbide containing crystalline substrate is provided. The method includes pyrolyzing a surface of the silicon carbide containing crystalline substrate to produce a silicon and carbon containing debris layer over the silicon carbide containing crystalline substrate, and removing the silicon and carbon containing debris layer, wherein the pyrolyzing and the removing is repeated at least once.