公开(公告)号：US10340334B2

公开(公告)日：2019-07-02

申请号：US15986942

申请日：2018-05-23

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Helmut Brech ,  Matthias Zigldrum ,  Michaela Braun ,  Christian Eckl

IPC: H01L29/06 ,  H01L21/265 ,  H01L21/768 ,  H01L23/528 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H01L29/40 ,  H03F1/02 ,  H03F3/193 ,  H01L23/48

Abstract: In an embodiment, a semiconductor device includes a semiconductor substrate having a bulk resistivity ρ≥100 Ohm.cm, a front surface and a rear surface. An LDMOS transistor is arranged in the semiconductor substrate. A RESURF structure including a doped buried layer is arranged in the semiconductor substrate. The LDMOS transistor includes a body contact region doped with a first conductivity type, and a source region disposed in the body contact region and doped with a second conductivity type opposite the first conductivity type. The source region includes a first well and a second well of the same second conductivity type. The first well is more highly doped than the second well. The first well extends from inside the body contact region to outside of a lateral extent of the body contact region in a direction towards a source side of a gate of the LDMOS transistor.

公开(公告)号：US20180350981A1

公开(公告)日：2018-12-06

申请号：US16100676

申请日：2018-08-10

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Helmut Brech ,  Matthias Zigldrum ,  Michaela Braun ,  Jan Ropohl

IPC: H01L29/78 ,  H01L23/532 ,  H01L23/522 ,  H01L21/768 ,  H01L29/10 ,  H01L29/66 ,  H01L23/528

CPC classification number: H01L29/7816 ,  H01L21/76804 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53295 ,  H01L29/1095 ,  H01L29/66681

Abstract: In an embodiment, a semiconductor device includes a semiconductor substrate having a front surface, a LDMOS transistor in the front surface, and a metallization structure arranged on the front surface. The metallization structure includes at least one cavity arranged in at least one dielectric layer. Related methods of manufacture are also described.

公开(公告)号：US20240030334A1

公开(公告)日：2024-01-25

申请号：US18352572

申请日：2023-07-14

Applicant: Infineon Technologies AG

Inventor： Helmut Brech ,  Albert Birner ,  Michaela Braun ,  Jan Ropohl ,  Matthias Zigldrum

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/40 ,  H01L29/417

CPC classification number: H01L29/7786 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/41758

Abstract: In an embodiment, a Group III nitride-based semiconductor device includes: a multilayer Group III nitride-based structure including a first major surface; and a source electrode, a gate electrode and a drain electrode arranged on the first major surface. The gate electrode is laterally arranged between the source electrode and the drain electrode and a metallization structure arranged on the first major surface. The metallization structure includes an electrically insulating layer arranged on the source electrode, the gate electrode and the drain electrode and a conductive redistribution structure electrically connected to the source electrode, the gate electrode and the drain electrode. One or more cavities are located in the electrically insulating layer of the metallization structure.

公开(公告)号：US10510626B2

公开(公告)日：2019-12-17

申请号：US15377371

申请日：2016-12-13

Applicant: Infineon Technologies AG

Inventor： Michaela Braun ,  Markus Menath

IPC: H01L21/66 ,  H01L21/78 ,  H01L21/683 ,  H01L21/3065

Abstract: In one embodiment, a wafer includes a number of die areas each including a semiconductor device and dedicated to become a separate die. The die areas are disposed on a first face of the wafer and wherein adjacent die areas are distanced from one another. A first trench and a second trench are formed on the first face between adjacent die areas. The first trench and the second trench are spaced apart from one another by a ridge. A third trench is disposed above the ridge on a second face of the wafer.

公开(公告)号：US20170373138A1

公开(公告)日：2017-12-28

申请号：US15458492

申请日：2017-03-14

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Helmut Brech ,  Matthias Zigldrum ,  Michaela Braun ,  Christian Eckl

IPC: H01L29/06 ,  H01L29/40 ,  H01L21/768 ,  H01L29/78 ,  H03F1/02 ,  H03F3/193

CPC classification number: H01L29/063 ,  H01L21/26513 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5283 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7823 ,  H03F1/0288 ,  H03F3/193 ,  H03F2200/451

Abstract: In an embodiment, a high frequency amplifying circuit includes a semiconductor device. The semiconductor device includes a semiconductor substrate having a bulk resistivity ρ≧100 Ohm·cm, a front surface and a rear surface, an LDMOS (Lateral Diffused Metal Oxide Semiconductor) transistor in the semiconductor substrate, and a RESURF structure comprising a doped buried layer arranged in the semiconductor substrate, spaced at a distance from the front surface and the rear surface, and coupled with at least one of a channel region and a body contact region of the LDMOS transistor.

公开(公告)号：US20170092552A1

公开(公告)日：2017-03-30

申请号：US15377371

申请日：2016-12-13

Applicant: Infineon Technologies AG

Inventor： Michaela Braun ,  Markus Menath

IPC: H01L21/66 ,  H01L21/683 ,  H01L21/3065 ,  H01L21/78

Abstract: In one embodiment, a wafer includes a number of die areas each including a semiconductor device and dedicated to become a separate die. The die areas are disposed on a first face of the wafer and wherein adjacent die areas are distanced from one another. A first trench and a second trench are formed on the first face between adjacent die areas. The first trench and the second trench are spaced apart from one another by a ridge. A third trench is disposed above the ridge on a second face of the wafer.

公开(公告)号：US10304789B2

公开(公告)日：2019-05-28

申请号：US15986433

申请日：2018-05-22

Applicant: Infineon Technologies AG

Inventor： Helmut Brech ,  Albert Birner ,  Matthias Zigldrum ,  Michaela Braun ,  Jan Ropohl

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/66 ,  H01L49/02 ,  H01L29/78 ,  H03F3/193 ,  H03F3/21 ,  H01L23/522

Abstract: In an embodiment, a method includes forming a first opening in a front surface of a semiconductor substrate including a LDMOS transistor structure, and covering the first opening with a first layer to form an enclosed cavity defined by material of the semiconductor substrate and the first layer. The material of the first layer lines sidewalls of the enclosed cavity.

公开(公告)号：US10020270B2

公开(公告)日：2018-07-10

申请号：US15279649

申请日：2016-09-29

Applicant: Infineon Technologies AG

Inventor： Helmut Brech ,  Albert Birner ,  Matthias Zigldrum ,  Michaela Braun ,  Jan Ropohl

IPC: H01L23/66 ,  H01L29/78 ,  H01L23/48 ,  H01L49/02 ,  H01L21/768 ,  H03F3/193 ,  H03F3/21

CPC classification number: H01L23/66 ,  H01L21/7682 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/522 ,  H01L28/10 ,  H01L28/20 ,  H01L28/40 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/7816 ,  H01L29/7835 ,  H01L2223/6616 ,  H01L2223/6644 ,  H01L2223/6655 ,  H01L2223/6683 ,  H03F3/193 ,  H03F3/21 ,  H03F2200/222 ,  H03F2200/411

Abstract: In an embodiment, a semiconductor device includes a semiconductor substrate including a front surface, an LDMOS transistor structure in the front surface, a conductive interconnection structure arranged on the front surface, and at least one cavity arranged in the front surface.

公开(公告)号：US09634085B1

公开(公告)日：2017-04-25

申请号：US15191854

申请日：2016-06-24

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Helmut Brech ,  Matthias Zigldrum ,  Michaela Braun ,  Christian Eckl

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/10 ,  H01L21/265 ,  H01L21/768 ,  H01L23/528

Abstract: In an embodiment, a semiconductor device includes a semiconductor substrate having a bulk resistivity ρ≧100 Ohm·cm, a front surface and a rear surface, at least one LDMOS transistor in the semiconductor substrate, and a RESURF structure. The RESURF structure includes a doped buried layer arranged in the semiconductor substrate, spaced at a distance from the front surface and the rear surface, and coupled with at least one of a channel region and a body contact region of the LDMOS transistor.

公开(公告)号：US09553022B1

公开(公告)日：2017-01-24

申请号：US14792419

申请日：2015-07-06

Applicant: Infineon Technologies AG

Inventor： Michaela Braun ,  Markus Menath

IPC: H01L21/00 ,  H01L21/78 ,  H01L21/66 ,  H01L23/31 ,  H01L21/683 ,  H01L21/3065

CPC classification number: H01L22/30 ,  H01L21/3065 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L22/34 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381

Abstract: In one embodiment, a wafer includes a number of die areas each including a semiconductor device and dedicated to become a separate die. The die areas are disposed on a first face of the wafer and wherein adjacent die areas are distanced from one another. A first trench and a second trench are formed on the first face between adjacent die areas. The first trench and the second trench are spaced apart from one another by a ridge. A third trench is disposed above the ridge on a second face of the wafer.

Abstract translation: 在一个实施例中，晶片包括多个管芯区域，每个管芯区域包括半导体器件，并专用于成为单独的管芯。 管芯区域设置在晶片的第一面上，并且其中相邻的管芯区域彼此间隔开。 第一沟槽和第二沟槽形成在相邻裸片区域之间的第一面上。 第一沟槽和第二沟槽通过脊彼此间隔开。 第三沟槽设置在晶片的第二面上的脊上方。