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    System and method to store data in an adjustably partitionable memory array
    11.
    发明授权
    System and method to store data in an adjustably partitionable memory array 有权
    将数据存储在可调节分区的存储器阵列中的系统和方法

    公开(公告)号：US09558114B2

    公开(公告)日：2017-01-31

    申请号：US13908040

    申请日：2013-06-03

    Applicant: Infineon Technologies AG

    Inventor： Rex Kho ,  Michael Hassel ,  Wolfgang Beck ,  Thomas Liebermann

    IPC: G06F12/06 ,  G11C8/12 ,  G11C16/24

    CPC classification number: G06F12/0646 ,  G11C8/12 ,  G11C16/24 ,  G11C2211/5641

    Abstract: The disclosure relates to an electronic memory system, and more specifically, to a system for storing data in an adjustably partitionable memory array, and a method to store data in an adjustably partitionable memory array. According to an embodiment of the disclosure, a system to store data in an adjustably partitionable memory array is provided, the system including a plurality of memory cells arranged in an array of rows and columns, a plurality of bit lines, and a plurality of switches, wherein each bit line is electrically coupled to a column of memory cells and each bit line comprises a switch configured to allow the respective bit line to be partitioned by opening of the switch.

    Abstract translation: 本公开涉及一种电子存储器系统，更具体地，涉及一种用于将数据存储在可调节分区存储器阵列中的系统，以及一种将数据存储在可调节分割存储器阵列中的方法。 根据本公开的实施例，提供了一种将数据存储在可调节的可分区存储器阵列中的系统，所述系统包括以行和列排列的多个存储器单元，多个位线和多个开关 ，其中每个位线电耦合到存储器单元的列，并且每个位线包括被配置为允许通过打开所述开关来分隔相应位线的开关。

    SYSTEM AND METHOD TO STORE DATA IN AN ADJUSTABLY PARTITIONABLE MEMORY ARRAY
    12.
    发明申请
    SYSTEM AND METHOD TO STORE DATA IN AN ADJUSTABLY PARTITIONABLE MEMORY ARRAY 有权
    在可调节的可分配存储器阵列中存储数据的系统和方法

    公开(公告)号：US20140359249A1

    公开(公告)日：2014-12-04

    申请号：US13908040

    申请日：2013-06-03

    Applicant: Infineon Technologies AG

    Inventor： Rex Kho ,  Michael Hassel ,  Wolfgang Beck ,  Thomas Liebermann

    IPC: G06F12/06

    CPC classification number: G06F12/0646 ,  G11C8/12 ,  G11C16/24 ,  G11C2211/5641

    Abstract: The disclosure relates to an electronic memory system, and more specifically, to a system for storing data in an adjustably partitionable memory array, and a method to store data in an adjustably partitionable memory array. According to an embodiment of the disclosure, a system to store data in an adjustably partitionable memory array is provided, the system including a plurality of memory cells arranged in an array of rows and columns, a plurality of bit lines, and a plurality of switches, wherein each bit line is electrically coupled to a column of memory cells and each bit line comprises a switch configured to allow the respective bit line to be partitioned by opening of the switch.

    Abstract translation: 本公开涉及一种电子存储器系统，更具体地，涉及一种用于将数据存储在可调节分区存储器阵列中的系统，以及一种将数据存储在可调节分割存储器阵列中的方法。 根据本公开的实施例，提供了一种将数据存储在可调节的可分区存储器阵列中的系统，所述系统包括以行和列排列的多个存储器单元，多个位线和多个开关 ，其中每个位线电耦合到存储器单元的列，并且每个位线包括被配置为允许通过打开所述开关来分隔相应位线的开关。

    Functional clock generation
    14.
    发明授权
    Functional clock generation 有权

    公开(公告)号：US10735006B1

    公开(公告)日：2020-08-04

    申请号：US16451317

    申请日：2019-06-25

    Applicant: Infineon Technologies AG

    Inventor： Rex Kho ,  Udo Elsholz

    IPC: H03L7/099 ,  G06F1/08

    Abstract: A functional clock generator, including: an oscillator configured to generate an oscillator clock having an oscillator clock frequency; a control value generator configured to generate control values to ramp the oscillator clock frequency between a first frequency and a second, higher frequency; a Phase-Locked Loop (PLL) configured to generate a PLL clock having the second frequency; and a selector configured to switch between selecting the oscillator clock and the PLL clock as a functional clock when the oscillator clock frequency and the PLL clock frequency are substantially equal.

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