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    DATA PROCESSING DEVICE
    1.
    发明公开
    DATA PROCESSING DEVICE 审中-公开

    公开(公告)号：US20230281117A1

    公开(公告)日：2023-09-07

    申请号：US18177934

    申请日：2023-03-03

    Applicant: Infineon Technologies AG

    Inventor： Ulrich Backhausen ,  Julie Henzler ,  Thomas Rabenalt

    IPC: G06F12/02

    CPC classification number: G06F12/0246

    Abstract: A method for dynamically activating a plurality of memory banks by way of a plurality of memory controllers in a chip, each of the memory banks being able to be read and written to independently of the other memory banks and each of the memory banks being able to be activatable by multiple of the plurality of memory controllers in each case. The method includes receiving information about an operating state of the chip, dynamically producing assignments of memory controllers to the memory banks based on the operating state of the chip, and activating the memory banks by way of the memory controllers in accordance with the produced assignments.

    Correction of bit errors
    2.
    发明授权
    Correction of bit errors 有权

    公开(公告)号：US11722153B2

    公开(公告)日：2023-08-08

    申请号：US17579721

    申请日：2022-01-20

    Applicant: Infineon Technologies AG

    Inventor： Thomas Kern ,  Michael Goessel ,  Thomas Rabenalt

    IPC: H03M13/00 ,  H03M13/15

    CPC classification number: H03M13/1575 ,  H03M13/152

    Abstract: Processing of a bit sequence is proposed, wherein (i) a first partial error syndrome s1 of an error syndrome and a second partial error syndrome s2 of the error syndrome are determined for the bit sequence, (ii) a first comparison value is determined on the basis of a bit position and the first partial error syndrome, (iii) a second comparison value is determined on the basis of the bit position and the second partial error syndrome, and (iv) the bit position is corrected should a comparison of the first comparison value with the second comparison value assume a specified value and otherwise the bit position is not corrected.

    Marker programming in non-volatile memories
    4.
    发明授权
    Marker programming in non-volatile memories 有权
    非易失性存储器中的标记编程

    公开(公告)号：US09405618B2

    公开(公告)日：2016-08-02

    申请号：US14289311

    申请日：2014-05-28

    Applicant: Infineon Technologies AG

    Inventor： Thomas Rabenalt ,  Ulrich Backhausen ,  Thomas Kern ,  Michael Goessel

    IPC: G06F11/10 ,  G11C29/52

    CPC classification number: G06F11/1068 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/1012 ,  G11C16/10 ,  G11C16/26 ,  G11C29/52 ,  G11C2029/0411 ,  H03M13/13

    Abstract: A method and a memory controller for accessing a non-volatile memory are disclosed. The method includes reading a first memory region of the non-volatile memory, ascertaining whether the first memory region contains a predetermined data pattern wherein the predetermined data pattern has no influence on resulting error correcting data determined for at least the first memory region. The method evaluating a data status for a second memory region of the non-volatile memory on the basis of a presence of the predetermined data pattern in the first memory region, wherein the data status indicates at least one of whether valid data is present within the second memory region and whether the second memory region is writable.

    Abstract translation: 公开了一种用于访问非易失性存储器的方法和存储器控制器。 该方法包括读取非易失性存储器的第一存储器区域，确定第一存储器区域是否包含预定数据模式，其中预定数据模式对至少第一存储区域确定的所得到的纠错数据没有影响。 该方法基于第一存储器区域中的预定数据模式的存在来评估非易失性存储器的第二存储器区域的数据状态，其中数据状态指示是否存在有效数据中的至少一个 第二存储器区域以及第二存储器区域是否可写入。

    Method of Detecting Bit Errors, An Electronic Circuit for Detecting Bit Errors, and a Data Storage Device
    5.
    发明申请
    Method of Detecting Bit Errors, An Electronic Circuit for Detecting Bit Errors, and a Data Storage Device 有权
    检测位错误的方法，用于检测位错误的电子电路和数据存储设备

    公开(公告)号：US20150100827A1

    公开(公告)日：2015-04-09

    申请号：US14045923

    申请日：2013-10-04

    Applicant: Infineon Technologies AG

    Inventor： Rex Kho ,  Thomas Rabenalt

    IPC: G06F11/07

    CPC classification number: G06F11/1024 ,  G06F11/08 ,  H03M13/03

    Abstract: A method of detecting bit errors in a data storage device is provided, which includes comparing a first bit sequence accessed during a read out operation of the data storage device with a second bit sequence that corresponds to an expected memory state of the data storage device.

    Abstract translation: 提供了一种检测数据存储装置中的比特错误的方法，其包括将在数据存储装置的读出操作期间访问的第一比特序列与对应于数据存储装置的预期存储状态的第二比特序列进行比较。

    METHOD FOR MEMORY STORAGE AND ACCESS
    6.
    发明公开
    METHOD FOR MEMORY STORAGE AND ACCESS 审中-公开

    公开(公告)号：US20240126640A1

    公开(公告)日：2024-04-18

    申请号：US18390065

    申请日：2023-12-20

    Applicant: Infineon Technologies AG

    Inventor： Thomas Kern ,  Thomas Rabenalt ,  Michael Goessel

    IPC: G06F11/08 ,  G06F11/10 ,  G11C29/18 ,  G11C29/42 ,  G11C29/44

    CPC classification number: G06F11/08 ,  G06F11/1012 ,  G11C29/18 ,  G11C29/42 ,  G11C29/4401

    Abstract: A method for storing data bits in memory cells, in which the data bits have at least one byte-filling bit, where at least one predefined functionality for a subset of the data bits is coded in the at least one byte-filling bit, and in which the data bits are stored in the memory cells. A method for reading data bits from memory cells, in which the data bits have at least one byte-filling bit, where at least one predefined functionality for a subset of the data bits is coded in the at least one byte-filling bit, and in which the data bits are read from the memory cells based on the coded predefined functionality. Corresponding apparatuses and memories are also disclosed.

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