APPARATUS AND METHOD FOR EFFICIENT GRAPHICS VIRTUALIZATION

    公开(公告)号:US20210201556A1

    公开(公告)日:2021-07-01

    申请号:US17141431

    申请日:2021-01-05

    Abstract: An apparatus and method are described for allocating local memories to virtual machines. For example, one embodiment of an apparatus comprises: a command streamer to queue commands from a plurality of virtual machines (VMs) or applications, the commands to be distributed from the command streamer and executed by graphics processing resources of a graphics processing unit (GPU); a tile cache to store graphics data associated with the plurality of VMs or applications as the commands are executed by the graphics processing resources; and tile cache allocation hardware logic to allocate a first portion of the tile cache to a first VM or application and a second portion of the tile cache to a second VM or application; the tile cache allocation hardware logic to further allocate a first region in system memory to store spill-over data when the first portion of the tile cache and/or the second portion of the file cache becomes full.

    APPARATUS AND METHOD FOR MANAGING DATA BIAS IN A GRAPHICS PROCESSING ARCHITECTURE

    公开(公告)号:US20190318446A1

    公开(公告)日:2019-10-17

    申请号:US16365056

    申请日:2019-03-26

    Abstract: An apparatus and method are described for managing data which is biased towards a processor or a GPU. For example, an apparatus comprises a processor comprising one or more cores, one or more cache levels, and cache coherence controllers to maintain coherent data in the one or more cache levels; a graphics processing unit (GPU) to execute graphics instructions and process graphics data, wherein the GPU and processor cores are to share a virtual address space for accessing a system memory; a GPU memory addressable through the virtual address space shared by the processor cores and GPU; and bias management circuitry to store an indication for whether the data has a processor bias or a GPU bias, wherein if the data has a GPU bias, the data is to be accessed by the GPU without necessarily accessing the processor's cache coherence controllers.

    PARALLEL DECOMPRESSION MECHANISM
    19.
    发明申请

    公开(公告)号:US20210149811A1

    公开(公告)日:2021-05-20

    申请号:US16685224

    申请日:2019-11-15

    Abstract: An apparatus to facilitate packing compressed data is disclosed. The apparatus includes compression hardware to compress memory data into a plurality of compressed data components and packing hardware to receive the plurality of compressed data components and pack a first of the plurality of compressed data components beginning at a least significant bit (LSB) location of a compressed bit stream and pack a second of the plurality of compressed data components beginning at a most significant bit (MSB) of the compressed bit stream.

Patent Agency Ranking