公开(公告)号：US20160365385A1

公开(公告)日：2016-12-15

申请号：US15247710

申请日：2016-08-25

Applicant: INTEL CORPORATION

Inventor： Ravi PILLARISETTY ,  Brian S. DOYLE ,  Elijah V. KARPOV ,  David L. KENCKE ,  Uday SHAH ,  Charles C. KUO ,  Robert S. CHAU

IPC: H01L27/24 ,  H01L29/78 ,  H01L45/00 ,  H01L29/66

CPC classification number: H01L27/2436 ,  H01L29/66477 ,  H01L29/66568 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1616 ,  H01L2029/7858

Abstract: An insulating layer is deposited over a transistor structure. The transistor structure comprises a gate electrode over a device layer on a substrate. The transistor structure comprises a first contact region and a second contact region on the device layer at opposite sides of the gate electrode. A trench is formed in the first insulating layer over the first contact region. A metal-insulator phase transition material layer with a S-shaped IV characteristic is deposited in the trench or in the via of the metallization layer above on the source side.

公开(公告)号：US20200161370A1

公开(公告)日：2020-05-21

申请号：US16630346

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Charles C. KUO

IPC: H01L27/24 ,  H01L45/00

Abstract: An integrated circuit comprising a self-aligned embedded phase change memory cell is described. In an example, the integrated circuit includes a bottom electrode. A conductive line is above the bottom electrode along a first direction above a substrate. A memory element is coupled between the bottom electrode and the conductive line, the memory element comprising a phase change material layer that is self-aligned with the conductive line.

公开(公告)号：US20170271576A1

公开(公告)日：2017-09-21

申请号：US15503680

申请日：2014-09-26

Applicant: Intel Corporation

Inventor： Kevin P. O'BRIEN ,  Kaan OGUZ ,  Brian S. DOYLE ,  Mark L. DOCZY ,  Charles C. KUO ,  Robert S. CHAU

IPC: H01L43/08 ,  H01L43/12 ,  H01L43/02 ,  G11C11/16 ,  H01L43/10

CPC classification number: H01L43/08 ,  G11C11/161 ,  G11C11/1659 ,  H01F10/3295 ,  H01L43/02 ,  H01L43/10 ,  H01L43/12

Abstract: A material layer stack for a magnetic tunneling junction, the material layer stack including a fixed magnetic layer; a dielectric layer; a free magnetic layer; and an amorphous electrically-conductive seed layer, wherein the fixed magnetic layer is disposed between the dielectric layer and the seed layer. A non-volatile memory device including a material stack including an amorphous electrically-conductive seed layer; and a fixed magnetic layer juxtaposed and in contact with the seed layer. A method including forming an amorphous seed layer on a first electrode of a memory device; forming a material layer stack on the amorphous seed layer, the material stack including a dielectric layer disposed between a fixed magnetic layer and a free magnetic layer, wherein the fixed magnetic layer.