公开(公告)号：US20160365385A1

公开(公告)日：2016-12-15

申请号：US15247710

申请日：2016-08-25

Applicant: INTEL CORPORATION

Inventor： Ravi PILLARISETTY ,  Brian S. DOYLE ,  Elijah V. KARPOV ,  David L. KENCKE ,  Uday SHAH ,  Charles C. KUO ,  Robert S. CHAU

IPC: H01L27/24 ,  H01L29/78 ,  H01L45/00 ,  H01L29/66

CPC classification number: H01L27/2436 ,  H01L29/66477 ,  H01L29/66568 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1616 ,  H01L2029/7858

Abstract: An insulating layer is deposited over a transistor structure. The transistor structure comprises a gate electrode over a device layer on a substrate. The transistor structure comprises a first contact region and a second contact region on the device layer at opposite sides of the gate electrode. A trench is formed in the first insulating layer over the first contact region. A metal-insulator phase transition material layer with a S-shaped IV characteristic is deposited in the trench or in the via of the metallization layer above on the source side.

公开(公告)号：US20150072490A1

公开(公告)日：2015-03-12

申请号：US14534088

申请日：2014-11-05

Applicant: Intel Corporation

Inventor： Brian S. DOYLE ,  Roza KOTLYAR ,  Uday SHAH ,  Charles C. KUO

IPC: H01L29/66 ,  H01L21/02

CPC classification number: H01L29/7827 ,  B82Y10/00 ,  H01L21/0237 ,  H01L21/02636 ,  H01L29/0669 ,  H01L29/0676 ,  H01L29/16 ,  H01L29/165 ,  H01L29/42376 ,  H01L29/42392 ,  H01L29/66431 ,  H01L29/66439 ,  H01L29/66666 ,  H01L29/775 ,  Y10S977/762

Abstract: Vertically oriented nanowire transistors including semiconductor layers or gate electrodes having compositions that vary over a length of the transistor. In embodiments, transistor channel regions are compositionally graded, or layered along a length of the channel to induce strain, and/or include a high mobility injection layer. In embodiments, a gate electrode stack including a plurality of gate electrode materials is deposited to modulate the gate electrode work function along the gate length.

Abstract translation: 垂直取向的纳米线晶体管包括具有在晶体管的长度上变化的组成的半导体层或栅电极。 在实施例中，晶体管沟道区域沿着沟道的长度成分地分级或分层以诱导应变，和/或包括高迁移率注入层。 在实施例中，沉积包括多个栅电极材料的栅极电极堆叠以沿着栅极长度调制栅电极功函数。

公开(公告)号：US20170365677A1

公开(公告)日：2017-12-21

申请号：US15673219

申请日：2017-08-09

Applicant: Intel Corporation

Inventor： Uday SHAH ,  Brian S. DOYLE ,  Justin K. BRASK ,  Robert S. CHAU ,  Thomas A. LETSON

IPC: H01L29/423 ,  H01L21/84 ,  H01L27/088 ,  H01L29/66 ,  H01L27/12 ,  H01L29/78 ,  H01L21/8234

CPC classification number: H01L29/42384 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/7854 ,  H01L29/7856 ,  H01L2924/13067 ,  Y10S438/978

Abstract: A nonplanar semiconductor device having a semiconductor body formed on an insulating layer of a substrate. The semiconductor body has a top surface opposite a bottom surface formed on the insulating layer and a pair of laterally opposite sidewalls wherein the distance between the laterally opposite sidewalls at the top surface is greater than at the bottom surface. A gate dielectric layer is formed on the top surface of the semiconductor body and on the sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric layer on the top surface and sidewalls of the semiconductor body. A pair of source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.

公开(公告)号：US20160043302A1

公开(公告)日：2016-02-11

申请号：US14887168

申请日：2015-10-19

Applicant: Intel Corporation

Inventor： Brian S. DOYLE ,  Charles C. KUO ,  David L. KENCKE ,  Roksana GOLIZADEH MOJARAD ,  Uday SHAH

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/12 ,  H01L43/08 ,  H01L43/10

CPC classification number: H01L43/02 ,  G11C11/155 ,  G11C11/161 ,  G11C11/1675 ,  H01L27/228 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

Abstract: Spin transfer torque memory (STTM) devices incorporating a field plate for application of an electric field to reduce a critical current required for transfer torque induced magnetization switching. Embodiments utilize not only current-induced magnetic filed or spin transfer torque, but also electric field induced manipulation of magnetic dipole orientation to set states in a magnetic device element (e.g., to write to a memory element). An electric field generated by a voltage differential between an MTJ electrode and the field plate applies an electric field to a free magnetic layer of a magnetic tunneling junction (MTJ) to modulate one or more magnetic properties over at least a portion of the free magnetic layer.

Abstract translation: 具有用于施加电场的场板的旋转转矩存储器（STTM）装置，以减少传递转矩感应磁化切换所需的临界电流。 实施例不仅利用电流感应磁场或自旋转移转矩，还利用电场诱导的磁偶极取向的操纵来设置磁性器件元件中的状态（例如，写入存储元件）。 由MTJ电极和场板之间的电压差产生的电场向磁性隧道结（MTJ）的自由磁性层施加电场，以在至少一部分自由磁性层上调制一个或多个磁性能 。

公开(公告)号：US20190214559A1

公开(公告)日：2019-07-11

申请号：US16099173

申请日：2016-07-02

Applicant: Intel Corporation

Inventor： James S. CLARKE ,  Ravi PILLARISETTY ,  Uday SHAH ,  Tejaswi K. INDUKURI ,  Niloy MUKHERJEE ,  Elijah V. KARPOV ,  Prashant MAJHI

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/146 ,  G11C13/0007 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/1266 ,  H01L45/1625 ,  H01L45/1633 ,  H01L45/1675

Abstract: Embodiments of the present invention include RRAM devices and their methods of fabrication. In an embodiment, a resistive random access memory (RRAM) cell includes a conductive interconnect disposed in a dielectric layer above a substrate. An RRAM device is coupled to the conductive interconnect. An RRAM memory includes a bottom electrode disposed above the conductive interconnect and on a portion of the dielectric layer. A conductive layer is formed on the bottom electrode layer. The conductive layer is separate and distinct from the bottom electrode layer. The conductive layer further includes a material that is different from the bottom electrode layer. A switching layer is formed on the conductive layer. An oxygen exchange layer is formed on the switching layer and a top electrode is formed on the oxygen exchange layer.

公开(公告)号：US20190066779A1

公开(公告)日：2019-02-28

申请号：US16080922

申请日：2016-04-01

Applicant: INTEL CORPORATION

Inventor： Elijah V. KARPOV ,  Ravi PILLARISETTY ,  Prashant MAJHI ,  Niloy MUKHERJEE ,  Uday SHAH

IPC: G11C13/00 ,  H01L27/24

CPC classification number: G11C13/0007 ,  G11C13/003 ,  G11C2213/15 ,  G11C2213/53 ,  G11C2213/73 ,  G11C2213/74 ,  G11C2213/79 ,  G11C2213/82 ,  H01L27/2445

Abstract: One embodiment provides an apparatus. The apparatus includes a bipolar junction transistor (BJT) and an integrated resistive element. The BJT includes a base contact, a base region, a collector contact, a collector region and an integrated emitter contact. The integrated resistive element includes a resistive layer and an integrated electrode. The resistive element is positioned between the base region and the integrated emitter contact.

公开(公告)号：US20180204842A1

公开(公告)日：2018-07-19

申请号：US15574092

申请日：2015-06-23

Applicant: Intel Corporation

Inventor： Elijah V. KARPOV ,  Jack T. KAVALIEROS ,  Robert S. CHAU ,  Niloy MUKHERJEE ,  Rafael RIOS ,  Prashant MAJHI ,  Van H. LE ,  Ravi PILLARISETTY ,  Uday SHAH ,  Gilbert DEWEY ,  Marko RADOSAVLJEVIC

IPC: H01L27/108 ,  H01L27/24 ,  H01L27/11551 ,  H01L27/1156 ,  H01L29/786 ,  H01L45/00 ,  G11C13/00

CPC classification number: H01L27/108 ,  G11C13/0007 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/1214 ,  H01L27/2436 ,  H01L27/2472 ,  H01L27/2481 ,  H01L29/7869 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/148 ,  H01L45/1625 ,  H01L45/1633

Abstract: A thin film transistor is deposited over a portion of a metal layer over a substrate. A memory element is coupled to the thin film transistor to provide a first memory cell. A second memory cell is over the first memory. A logic block is coupled to at least the first memory cell.