公开(公告)号：US20200303502A1

公开(公告)日：2020-09-24

申请号：US16361861

申请日：2019-03-22

Applicant: Intel Corporation

Inventor： Cory BOMBERGER ,  Anand MURTHY ,  Mark T. BOHR ,  Tahir GHANI ,  Biswajeet GUHA

IPC: H01L29/08 ,  H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L29/417

Abstract: Gate-all-around integrated circuit structures having source or drain structures with epitaxial nubs, and methods of fabricating gate-all-around integrated circuit structures having source or drain structures with epitaxial nubs, are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires and a second vertical arrangement of horizontal nanowires. A first pair of epitaxial source or drain structures includes vertically discrete portions aligned with the first vertical arrangement of horizontal nanowires. A second pair of epitaxial source or drain structures includes vertically discrete portions aligned with the second vertical arrangement of horizontal nanowires. A conductive contact structure is laterally between and in contact with the one of the first pair of epitaxial source or drain structures and the one of the second pair of epitaxial source or drain structures.

公开(公告)号：US20200006504A1

公开(公告)日：2020-01-02

申请号：US16022502

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Cory BOMBERGER ,  Rishabh MEHANDRU ,  Anupama BOWONDER ,  Biswajeet GUHA ,  Anand MURTHY ,  Tahir GHANI

IPC: H01L29/417 ,  H01L29/08 ,  H01L29/78 ,  H01L29/66 ,  H01L29/167

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, integrated circuit structures having source or drain structures with a contact etch stop layer are described. In an example, an integrated circuit structure includes a fin including a semiconductor material, the fin having a lower fin portion and an upper fin portion. A gate stack is over the upper fin portion of the fin, the gate stack having a first side opposite a second side. A first epitaxial source or drain structure is embedded in the fin at the first side of the gate stack. A second epitaxial source or drain structure is embedded in the fin at the second side of the gate stack, the first and second epitaxial source or drain structures including a lower semiconductor layer, an intermediate semiconductor layer and an upper semiconductor layer.

公开(公告)号：US20200006332A1

公开(公告)日：2020-01-02

申请号：US16024671

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Cory BOMBERGER ,  Anand MURTHY ,  Stephen CEA ,  Biswajeet GUHA ,  Anupama BOWONDER ,  Tahir GHANI

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/267 ,  H01L29/08

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, integrated circuit structures having channel structures with sub-fin dopant diffusion blocking layers are described. In an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. The lower fin portion includes a dopant diffusion blocking layer on a first semiconductor layer doped to a first conductivity type. The upper fin portion includes a portion of a second semiconductor layer, the second semiconductor layer on the dopant diffusion blocking layer. An isolation structure is along sidewalls of the lower fin portion. A gate stack is over a top of and along sidewalls of the upper fin portion, the gate stack having a first side opposite a second side. A first source or drain structure at the first side of the gate stack.

公开(公告)号：US20230343826A1

公开(公告)日：2023-10-26

申请号：US18216563

申请日：2023-06-29

Applicant: Intel Corporation

Inventor： Cory BOMBERGER ,  Anand MURTHY ,  Anupama BOWONDER ,  Aaron BUDREVICH ,  Tahir GHANI

IPC: H01L29/08 ,  H01L29/161 ,  H01L29/167 ,  H01L29/66 ,  H01L21/02 ,  H01L29/78

CPC classification number: H01L29/0847 ,  H01L29/161 ,  H01L29/167 ,  H01L29/66636 ,  H01L21/02532 ,  H01L21/02579 ,  H01L29/66795 ,  H01L29/7851

Abstract: Embodiments of the disclosure include integrated circuit structures having source or drain dopant diffusion blocking layers. In an example, an integrated circuit structure includes a fin including silicon. A gate structure is over a channel region of the fin, the gate structure having a first side opposite a second side. A first source or drain structure is at the first side of the gate structure. A second source or drain structure is at the second side of the gate structure. The first and second source or drain structures include a first semiconductor layer and a second semiconductor layer. The first semiconductor layer is in contact with the channel region of the fin, and the second semiconductor layer is on the first semiconductor layer. The first semiconductor layer has a greater concentration of germanium than the second semiconductor layer, and the second semiconductor layer includes boron dopant impurity atoms.

公开(公告)号：US20230275157A1

公开(公告)日：2023-08-31

申请号：US18143549

申请日：2023-05-04

Applicant: Intel Corporation

Inventor： Cory BOMBERGER ,  Anand S. MURTHY ,  Tahir GHANI ,  Anupama BOWONDER

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/165

CPC classification number: H01L29/7853 ,  H01L29/66818 ,  H01L29/165 ,  H01L29/7851

Abstract: Fin smoothing, and integrated circuit structures resulting therefrom, are described. For example, an integrated circuit structure includes a semiconductor fin having a protruding fin portion above an isolation structure, the protruding fin portion having substantially vertical sidewalls. The semiconductor fin further includes a sub-fin portion within an opening in the isolation structure, the sub-fin portion having a different semiconductor material than the protruding fin portion. The sub-fin portion has a width greater than or less than a width of the protruding portion where the sub-fin portion meets the protruding portion. A gate stack is over and conformal with the protruding fin portion of the semiconductor fin. A first source or drain region at a first side of the gate stack, and a second source or drain region at a second side of the gate stack opposite the first side of the gate stack.

公开(公告)号：US20230087399A1

公开(公告)日：2023-03-23

申请号：US17482880

申请日：2021-09-23

Applicant: Intel Corporation

Inventor： Debaleena NANDI ,  Cory BOMBERGER ,  Rushabh SHAH ,  Gilbert DEWEY ,  Nazila HARATIPOUR ,  Mauro J. KOBRINSKY ,  Anand S. MURTHY ,  Tahir GHANI

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

Abstract: Gate-all-around integrated circuit structures having confined epitaxial source or drain structures, are described. For example, an integrated circuit structure includes a plurality of nanowires above a sub-fin. A gate stack is over the plurality of nanowires and the sub-fin. Epitaxial source or drain structures are on opposite ends of the plurality of nanowires. The epitaxial source or drain structures comprise i) a first PMOS epitaxial (pEPI) region of germanium and boron, ii) a second pEPI region of silicon, germanium and boron on the first pEPI region at a contact location, iii) a capping layer comprising silicon over the second pEPI region. A conductive contact material comprising titanium is on the capping layer.

公开(公告)号：US20220416050A1

公开(公告)日：2022-12-29

申请号：US17359327

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Debaleena NANDI ,  Cory BOMBERGER ,  Gilbert DEWEY ,  Anand S. MURTHY ,  Mauro KOBRINSKY ,  Rushabh SHAH ,  Chi-Hing CHOI ,  Harold W. KENNEL ,  Omair SAADAT ,  Adedapo A. ONI ,  Nazila HARATIPOUR ,  Tahir GHANI

IPC: H01L29/45 ,  H01L29/08 ,  H01L29/161 ,  H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

Abstract: Embodiments disclosed herein include semiconductor devices with improved contact resistances. In an embodiment, a semiconductor device comprises a semiconductor channel, a gate stack over the semiconductor channel, a source region on a first end of the semiconductor channel, a drain region on a second end of the semiconductor channel, and contacts over the source region and the drain region. In an embodiment, the contacts comprise a silicon germanium layer, an interface layer over the silicon germanium layer, and a titanium layer over the interface layer.

公开(公告)号：US20200312960A1

公开(公告)日：2020-10-01

申请号：US16369760

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Cory BOMBERGER ,  Anand MURTHY ,  Susmita GHOSE ,  Siddharth CHOUKSEY

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/32 ,  H01L29/165 ,  H01L29/167 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/306

Abstract: Gate-all-around integrated circuit structures having embedded GeSnB source or drain structures, and methods of fabricating gate-all-around integrated circuit structures having embedded GeSnB source or drain structures, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires above a fin, the fin including a defect modification layer on a first semiconductor layer, and a second semiconductor layer on the defect modification layer. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires, and a second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires.

公开(公告)号：US20200312959A1

公开(公告)日：2020-10-01

申请号：US16368097

申请日：2019-03-28

Applicant: Intel Corporation

Inventor： Cory BOMBERGER ,  Anand MURTHY ,  Suresh VISHWANATH

IPC: H01L29/08 ,  H01L29/78 ,  H01L29/66 ,  H01L29/16 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/06 ,  H01L21/02 ,  H01L23/00

Abstract: Integrated circuit structures having source or drain structures with low resistivity are described. In an example, integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. A gate stack is over the upper fin portion of the fin, the gate stack having a first side opposite a second side. A first source or drain structure includes an epitaxial structure embedded in the fin at the first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at the second side of the gate stack. Each epitaxial structure of the first and second source or drain structures include silicon, germanium and boron. The first and second source or drain structures have a resistivity less than or equal to 0.3 mOhm·cm.

公开(公告)号：US20200219975A1

公开(公告)日：2020-07-09

申请号：US16238858

申请日：2019-01-03

Applicant: Intel Corporation

Inventor： Cory BOMBERGER ,  Anand MURTHY ,  Anupama BOWONDER ,  Aaron BUDREVICH ,  Tahir GHANI

IPC: H01L29/08 ,  H01L29/161 ,  H01L29/167 ,  H01L29/78 ,  H01L21/02 ,  H01L29/66

Abstract: Embodiments of the disclosure include integrated circuit structures having source or drain dopant diffusion blocking layers. In an example, an integrated circuit structure includes a fin including silicon. A gate structure is over a channel region of the fin, the gate structure having a first side opposite a second side. A first source or drain structure is at the first side of the gate structure. A second source or drain structure is at the second side of the gate structure. The first and second source or drain structures include a first semiconductor layer and a second semiconductor layer. The first semiconductor layer is in contact with the channel region of the fin, and the second semiconductor layer is on the first semiconductor layer. The first semiconductor layer has a greater concentration of germanium than the second semiconductor layer, and the second semiconductor layer includes boron dopant impurity atoms.