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公开(公告)号：US20200151364A1
公开(公告)日：2020-05-14
申请号：US16680315
申请日：2019-11-11
申请人： Intel Corporation
IPC分类号： G06F21/70
摘要： A system-on-chip (SoC) includes a host CPU on a CPU fabric, the host CPU including multiple processor cores, each associated with multiple security attributes. The SoC includes a secure asset on a network-on-chip and a security co-processor. The security co-processor includes circuitry to detect requests from the processor cores targeting the secure asset and security function processing requests, to determine, based on associated security attributes, whether the core or function is authorized to access the secure asset, to allow the request to be issued, if the core or function is so authorized, and to prevent its issuance, if not. The determination may be dependent on a signal from the CPU fabric indicating whether the host CPU can modify its security attributes or they are locked down. The security co-processor may have the highest security level and may be the only master on the SoC that can access the secure asset.
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公开(公告)号：US20200183482A1
公开(公告)日：2020-06-11
申请号：US16370572
申请日：2019-03-29
申请人： Intel Corporation
发明人： Julien Sebot , Rangeen Basu Roy Chowdhury , Rustam Miftakhutdinov , Stephen J. Tarsa , Gautham N. Chinya , Eric Donkoh
IPC分类号： G06F1/3234 , G06F1/3296 , G06F1/324 , G06F1/3228 , G06F9/50 , G06N5/04 , G06N20/00
摘要： A system on a chip is described that comprises a processor and a set of memory components that store instructions, which when executed by the processor cause the system on a chip to: generate, by a set of data collectors of a telemetry subsystem, a set of streams of telemetry metadata describing operation of the processor, forward one or more streams of telemetry metadata from the set of streams of telemetry metadata to a set of machine learning-driven adaptation decision models, receive, from the set of machine learning-driven adaptation decision models, a set of configuration parameters for controlling operation of the processor based on the one or more streams of telemetry metadata, and modify operation of the processor based on the set of configuration parameters.
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公开(公告)号：US10305976B2
公开(公告)日：2019-05-28
申请号：US14860241
申请日：2015-09-21
申请人： Intel Corporation
发明人： Chit Kwan Lin , Arnab Paul , Gautham N. Chinya
IPC分类号： G06F15/173 , H04L29/08
摘要： A method for managing computing includes replicating a subset of a machine state of a first computing device onto a second computing device, wherein the subset of the machine state is required to execute machine code. Execution of the machine code is offloaded to the second computing device.
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公开(公告)号：US10158582B2
公开(公告)日：2018-12-18
申请号：US14828301
申请日：2015-08-17
申请人： INTEL CORPORATION
发明人： Thomas J. Hernandez , Gustavo D. Domingo Yaguez , Marci Meingast , Aras Bilgen , Davi I. Shaw , Gautham N. Chinya
IPC分类号： G06F15/16 , H04L12/911 , H04L29/08 , H04W4/12 , H04W76/14 , H04L29/06 , G06F21/33 , G06F21/44 , H04W12/04 , H04W76/02 , H04W72/04
摘要： Embodiments of techniques and systems associated with device-to-device (D2D) resource sharing are described. In some embodiments, a D2D communication channel between a first device and a second device is established and a sharing request is received at the first device, from the second device, including a credential identifying the second device. Data representative of a first resource locally available to the first device, but not locally available to the second device, is provided to the second device by the first device. Use of the first resource may be controlled in accordance with an instruction transmitted to the first device from the second device. Other embodiments may be described and/or claimed.
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公开(公告)号：US20180246762A1
公开(公告)日：2018-08-30
申请号：US15444390
申请日：2017-02-28
申请人： Intel Corporation
IPC分类号： G06F9/50
CPC分类号： G06F9/5083
摘要： In one embodiment, a processor comprises a processor optimization unit. The processor optimization unit is to collect runtime information associated with a computing device, wherein the runtime information comprises information indicating a performance of the computing device during program execution. The processor optimization unit is further to receive runtime optimization information for the computing device, wherein the runtime optimization information comprises information associated with one or more runtime optimizations for the computing device, and wherein the runtime optimization information is determined based on an analysis of the collected runtime information. The processor optimization unit is further to perform the one or more runtime optimizations for the computing device based on the runtime optimization information.
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16.发明申请MECHANISM FOR INSTRUCTION SET BASED THREAD EXECUTION ON A PLURALITY OF INSTRUCTION SEQUENCERS 审中-公开用于指导性设计的机构执行多个指令序列公开(公告)号：US20170010895A1
公开(公告)日：2017-01-12
申请号：US15276290
申请日：2016-09-26
申请人： Intel Corporation
发明人： Hong Wang , John P. Shen , Edward T. Grochowski , Richard A. Hankins , Gautham N. Chinya , Bryant E. Bigbee , Shivnandan D. Kaushik , Xiang Chris Zou , Per Hammarlund , Scott Dion Rodgers , Xinmin Tian , Anil Aggarwal , Prashant Sethi , Baiju V. Patel , James P. Held
CPC分类号： G06F9/3867 , G06F9/30003 , G06F9/30043 , G06F9/3005 , G06F9/3009 , G06F9/30145 , G06F9/3017 , G06F9/30174 , G06F9/3851 , G06F9/4843 , G06F9/4881
摘要： In an embodiment, a method is provided. The method includes managing user-level threads on a first instruction sequencer in response to executing user-level instructions on a second instruction sequencer that is under control of an application level program. A first user-level thread is run on the second instruction sequencer and contains one or more user level instructions. A first user level instruction has at least 1) a field that makes reference to one or more instruction sequencers or 2) implicitly references with a pointer to code that specifically addresses one or more instruction sequencers when the code is executed.
摘要翻译： 在一个实施例中，提供了一种方法。 该方法包括响应于在应用级程序的控制下对第二指令定序器执行用户级指令来管理第一指令定序器上的用户级线程。 在第二指令定序器上运行第一用户级线程并且包含一个或多个用户级指令。 第一用户级指令至少具有1）引用一个或多个指令定序器的字段，或者2）使用指向代码执行代码时特定寻址一个或多个指令定序器的代码的指针进行隐式引用。
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公开(公告)号：US20160105375A1
公开(公告)日：2016-04-14
申请号：US14828301
申请日：2015-08-17
申请人： INTEL CORPORATION
发明人： Thomas J. Hernandez , Gustavo D. Domingo Yaguez , Marci Meingast , Aras Bilgen , Davi I. Shaw , Gautham N. Chinya
IPC分类号： H04L12/911 , H04L29/06
CPC分类号： H04L47/82 , G06F21/335 , G06F21/445 , H04L29/08072 , H04L63/061 , H04L63/101 , H04L63/18 , H04L65/1069 , H04L67/1076 , H04W4/12 , H04W12/04 , H04W72/0406 , H04W76/14
摘要： Embodiments of techniques and systems associated with device-to-device (D2D) resource sharing are described. In some embodiments, a D2D communication channel between a first device and a second device is established and a sharing request is received at the first device, from the second device, including a credential identifying the second device. Data representative of a first resource locally available to the first device, but not locally available to the second device, is provided to the second device by the first device. Use of the first resource may be controlled in accordance with an instruction transmitted to the first device from the second device. Other embodiments may be described and/or claimed.
摘要翻译： 描述了与设备到设备（D2D）资源共享相关联的技术和系统的实施例。 在一些实施例中，建立第一设备和第二设备之间的D2D通信信道，并且从第二设备在第一设备处接收共享请求，包括识别第二设备的凭证。 通过第一设备向第二设备提供代表第一设备本地可用的但不能本地可用于第二设备的第一资源的数据。 可以根据从第二设备发送到第一设备的指令来控制第一资源的使用。 可以描述和/或要求保护其他实施例。
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公开(公告)号：US09112884B2
公开(公告)日：2015-08-18
申请号：US13997636
申请日：2013-03-13
申请人： INTEL CORPORATION
发明人： Thomas J. Hernandez , Gustavo D. Domingo Yaguez , Marci Meingast , Aras Bilgen , Davi I. Shaw , Gautham N. Chinya
CPC分类号： H04L47/82 , G06F21/335 , G06F21/445 , H04L29/08072 , H04L63/061 , H04L63/101 , H04L63/18 , H04L65/1069 , H04L67/1076 , H04W4/12 , H04W12/04 , H04W72/0406 , H04W76/14
摘要： Embodiments of techniques and systems associated with device-to-device (D2D) resource sharing are described. In some embodiments, a D2D communication channel between a first device and a second device is established and a sharing request is received at the first device, from the second device, including a credential identifying the second device. Data representative of a first resource locally available to the first device, but not locally available to the second device, is provided to the second device by the first device. Use of the first resource may be controlled in accordance with an instruction transmitted to the first device from the second device. Other embodiments may be described and/or claimed.
摘要翻译： 描述了与设备到设备（D2D）资源共享相关联的技术和系统的实施例。 在一些实施例中，建立第一设备和第二设备之间的D2D通信信道，并且从第二设备在第一设备处接收共享请求，包括识别第二设备的凭证。 通过第一设备向第二设备提供代表第一设备本地可用的但不能本地可用于第二设备的第一资源的数据。 可以根据从第二设备发送到第一设备的指令来控制第一资源的使用。 可以描述和/或要求保护其他实施例。
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公开(公告)号：US11010166B2
公开(公告)日：2021-05-18
申请号：US15087854
申请日：2016-03-31
申请人： Intel Corporation
发明人： Debabrata Mohapatra , Perry H. Wang , Xiang Zou , Sang Kyun Kim , Deepak A. Mathaikutty , Gautham N. Chinya
摘要： A processor includes a front end including circuitry to decode a first instruction to set a performance register for an execution unit and a second instruction, and an allocator including circuitry to assign the second instruction to the execution unit to execute the second instruction. The execution unit includes circuitry to select between a normal computation and an accelerated computation based on a mode field of the performance register, perform the selected computation, and select between a normal result associated with the normal computation and an accelerated result associated with the accelerated computation based on the mode field.
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公开(公告)号：US10534935B2
公开(公告)日：2020-01-14
申请号：US15200935
申请日：2016-07-01
申请人： Intel Corporation
IPC分类号： G06F21/70
摘要： A system-on-chip (SoC) includes a host CPU on a CPU fabric, the host CPU including multiple processor cores, each associated with multiple security attributes. The SoC includes a secure asset on a network-on-chip and a security co-processor. The security co-processor includes circuitry to detect requests from the processor cores targeting the secure asset and security function processing requests, to determine, based on associated security attributes, whether the core or function is authorized to access the secure asset, to allow the request to be issued, if the core or function is so authorized, and to prevent its issuance, if not. The determination may be dependent on a signal from the CPU fabric indicating whether the host CPU can modify its security attributes or they are locked down. The security co-processor may have the highest security level and may be the only master on the SoC that can access the secure asset.
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