公开(公告)号：US20200212211A1

公开(公告)日：2020-07-02

申请号：US16643923

申请日：2017-09-30

Applicant: Intel Corporation

Inventor： Marko Radosavljevic ,  Sansaptak Dasgupta ,  Han Wui Then ,  Ibrahim Ban ,  Paul B. Fischer

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/08 ,  H01L29/205 ,  H01L29/51 ,  H01L29/66 ,  H01L21/02 ,  H01L21/306 ,  H01L21/762

Abstract: A device including a III-N material is described. The device includes a transistor structure having a first layer including a first group III-nitride (III-N) material, a polarization charge inducing layer above the first layer, the polarization charge inducing layer including a second III-N material, a gate electrode above the polarization charge inducing layer and a source structure and a drain structure on opposite sides of the gate electrode. The device further includes a plurality of peripheral structures adjacent to transistor structure, where each of the peripheral structure includes the first layer, but lacks the polarization charge inducing layer, an insulating layer above the peripheral structure and the transistor structure, wherein the insulating layer includes a first dielectric material. A metallization structure, above the peripheral structure, is coupled to the transistor structure.

公开(公告)号：US10381350B2

公开(公告)日：2019-08-13

申请号：US16151175

申请日：2018-10-03

Applicant: Intel Corporation

Inventor： Peter L. D. Chang ,  Uygar E. Avci ,  David Kencke ,  Ibrahim Ban

IPC: H01L21/00 ,  H01L21/84 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/108 ,  H01L27/12 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28 ,  H01L27/092 ,  H01L29/06 ,  H01L29/49 ,  H01L29/51 ,  H01L29/16

Abstract: A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.

公开(公告)号：US10121792B2

公开(公告)日：2018-11-06

申请号：US15727918

申请日：2017-10-09

Applicant: Intel Corporation

Inventor： Peter L. D. Chang ,  Uygar E. Avci ,  David Kencke ,  Ibrahim Ban

IPC: H01L21/00 ,  H01L21/84 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/108 ,  H01L29/06 ,  H01L29/49 ,  H01L29/78 ,  H01L29/51

Abstract: A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.

公开(公告)号：US09618824B2

公开(公告)日：2017-04-11

申请号：US14499115

申请日：2014-09-27

Applicant: Intel Corporation

Inventor： Edris M. Mohammed ,  Ibrahim Ban

IPC: G02F1/35 ,  H01L31/14 ,  G01V8/00

CPC classification number: G02F1/353 ,  A61B5/1135 ,  A61B5/14532 ,  G01N21/3586 ,  G01N2021/1793 ,  G01V8/005 ,  G02F2203/13 ,  H01L31/14

Abstract: Systems and methods may provide for an integrated miniature sensor that operates in the Terahertz region of the electromagnetic spectrum. The integrated miniature sensor may detect a remote target and operate in a non-contact, non-invasive manner. Numerous signal analysis techniques may be employed such as Doppler radar technology, absorption spectroscopy, and others when the integrated miniature sensor is used in biomedical, physiological and other settings where prolonged recording of bio-signals is needed.

公开(公告)号：US09275999B2

公开(公告)日：2016-03-01

申请号：US14641167

申请日：2015-03-06

Applicant: Intel Corporation

Inventor： Peter L. D. Chang ,  Uygar E. Avci ,  David Kencke ,  Ibrahim Ban

IPC: H01L21/336 ,  H01L27/088 ,  H01L27/108 ,  H01L27/12 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28

CPC classification number: H01L27/10802 ,  H01L21/28008 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823857 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0924 ,  H01L27/0928 ,  H01L27/108 ,  H01L27/10826 ,  H01L27/10844 ,  H01L27/10879 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/16 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/517 ,  H01L29/66477 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7841 ,  H01L29/785 ,  H01L29/7851 ,  Y10S257/903

Abstract: A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.