公开(公告)号：US11785759B2

公开(公告)日：2023-10-10

申请号：US17894968

申请日：2022-08-24

Applicant: Intel Corporation

Inventor： Peter L. D. Chang ,  Uygar E. Avci ,  David Kencke ,  Ibrahim Ban

IPC: H10B12/00 ,  H01L27/12 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/49 ,  H01L29/51 ,  H01L29/16

CPC classification number: H10B12/20 ,  H01L21/28008 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823857 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0924 ,  H01L27/0928 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/16 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/517 ,  H01L29/66477 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7841 ,  H01L29/7851 ,  H10B12/00 ,  H10B12/01 ,  H10B12/36 ,  H10B12/056 ,  Y10S257/903

Abstract: A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.

公开(公告)号：US09939578B2

公开(公告)日：2018-04-10

申请号：US13891543

申请日：2013-05-10

Applicant: Intel Corporation

Inventor： Peter L. D. Chang ,  Jai-Hung Tseng

IPC: G02B6/12 ,  G02B6/138 ,  G02B6/42

CPC classification number: G02B6/12 ,  G02B6/138 ,  G02B6/4204 ,  G02B6/4212 ,  G02B2006/12171 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014

Abstract: Planar lightwave circuits with a polymer coupling waveguide optically coupling a planar waveguide over a first region of a substrate to an optical component, such as a laser, affixed to a second region of the substrate. The coupling waveguide may be formed from a polymer layer applied over the planar waveguide and optical component such that any misalignment between the two may be accommodated by patterning the polymer into a waveguide having a first end aligned to an end of the planar waveguide and a second end aligned to an edge of the optical component. In embodiments, the polymer is photo-definable, such as a negative resist, and may be patterned through direct laser writing. In embodiments, the optical component is a thin film affixed to the substrate through micro-transfer printing. In other embodiments, the optical component is a semiconductor chip affixed to the substrate by flip-chip bonding.

公开(公告)号：US09250406B2

公开(公告)日：2016-02-02

申请号：US13722951

申请日：2012-12-20

Applicant: INTEL CORPORATION

Inventor： Peter L. D. Chang ,  Edris M. Mohammed ,  Henning Braunisch ,  Hengju Cheng

IPC: G02B6/12 ,  G02B6/43

CPC classification number: G02B6/43 ,  H01L2224/73204 ,  Y10T29/49117 ,  Y10T29/4913

Abstract: Embodiments of the present disclosure provide techniques and configurations for routing signals of an electro-optical assembly using a glass bridge. In one embodiment, an electro-optical assembly includes a laser die having a laser device and a glass bridge electrically coupled with the laser die by one or more interconnect structures, the glass bridge including electrical routing features configured to route electrical signals to the laser die from a transmitter device. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例提供了使用玻璃桥路由电光学组件路由信号的技术和配置。 在一个实施例中，电光学组件包括具有激光器件的激光器管芯和通过一个或多个互连结构与激光管芯电耦合的玻璃桥，所述玻璃桥接器包括被配置为将电信号路由到激光器管芯 从发射机设备。 可以描述和/或要求保护其他实施例。

公开(公告)号：US20170207222A1

公开(公告)日：2017-07-20

申请号：US15474689

申请日：2017-03-30

Applicant: Intel Corporation

Inventor： Peter L. D. Chang ,  Uygar E. Avci ,  David Kencke ,  Ibrahim Ban

IPC: H01L27/108 ,  H01L29/51 ,  H01L29/49 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L27/10802 ,  H01L21/28008 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823857 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0924 ,  H01L27/0928 ,  H01L27/108 ,  H01L27/10826 ,  H01L27/10844 ,  H01L27/10879 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/16 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/517 ,  H01L29/66477 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7841 ,  H01L29/785 ,  H01L29/7851 ,  Y10S257/903

Abstract: A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.

公开(公告)号：US11462540B2

公开(公告)日：2022-10-04

申请号：US17142176

申请日：2021-01-05

Applicant: Intel Corporation

Inventor： Peter L. D. Chang ,  Uygar E. Avci ,  David Kencke ,  Ibrahim Ban

IPC: H01L21/00 ,  H01L21/84 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/108 ,  H01L27/12 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28 ,  H01L27/092 ,  H01L29/06 ,  H01L29/49 ,  H01L29/51 ,  H01L29/16

Abstract: A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.

公开(公告)号：US10720434B2

公开(公告)日：2020-07-21

申请号：US16452469

申请日：2019-06-25

Applicant: Intel Corporation

Inventor： Peter L. D. Chang ,  Uygar E. Avci ,  David Kencke ,  Ibrahim Ban

IPC: H01L21/00 ,  H01L21/84 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/108 ,  H01L27/12 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28 ,  H01L27/092 ,  H01L29/06 ,  H01L29/49 ,  H01L29/51 ,  H01L29/16

Abstract: A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.

公开(公告)号：US10381350B2

公开(公告)日：2019-08-13

申请号：US16151175

申请日：2018-10-03

Applicant: Intel Corporation

Inventor： Peter L. D. Chang ,  Uygar E. Avci ,  David Kencke ,  Ibrahim Ban

IPC: H01L21/00 ,  H01L21/84 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/108 ,  H01L27/12 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28 ,  H01L27/092 ,  H01L29/06 ,  H01L29/49 ,  H01L29/51 ,  H01L29/16

Abstract: A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.

公开(公告)号：US10121792B2

公开(公告)日：2018-11-06

申请号：US15727918

申请日：2017-10-09

Applicant: Intel Corporation

Inventor： Peter L. D. Chang ,  Uygar E. Avci ,  David Kencke ,  Ibrahim Ban

IPC: H01L21/00 ,  H01L21/84 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/108 ,  H01L29/06 ,  H01L29/49 ,  H01L29/78 ,  H01L29/51

Abstract: A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.

公开(公告)号：US09275999B2

公开(公告)日：2016-03-01

申请号：US14641167

申请日：2015-03-06

Applicant: Intel Corporation

Inventor： Peter L. D. Chang ,  Uygar E. Avci ,  David Kencke ,  Ibrahim Ban

IPC: H01L21/336 ,  H01L27/088 ,  H01L27/108 ,  H01L27/12 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28

CPC classification number: H01L27/10802 ,  H01L21/28008 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823857 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0924 ,  H01L27/0928 ,  H01L27/108 ,  H01L27/10826 ,  H01L27/10844 ,  H01L27/10879 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/16 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/517 ,  H01L29/66477 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7841 ,  H01L29/785 ,  H01L29/7851 ,  Y10S257/903

Abstract: A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.

公开(公告)号：US10916547B2

公开(公告)日：2021-02-09

申请号：US16900359

申请日：2020-06-12

Applicant: Intel Corporation

Inventor： Peter L. D. Chang ,  Uygar E. Avci ,  David Kencke ,  Ibrahim Ban

IPC: H01L21/00 ,  H01L21/84 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/108 ,  H01L27/12 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28 ,  H01L27/092 ,  H01L29/06 ,  H01L29/49 ,  H01L29/51 ,  H01L29/16

Abstract: A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.