公开(公告)号：US11785759B2

公开(公告)日：2023-10-10

申请号：US17894968

申请日：2022-08-24

Applicant: Intel Corporation

Inventor： Peter L. D. Chang ,  Uygar E. Avci ,  David Kencke ,  Ibrahim Ban

IPC: H10B12/00 ,  H01L27/12 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/49 ,  H01L29/51 ,  H01L29/16

CPC classification number: H10B12/20 ,  H01L21/28008 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823857 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0924 ,  H01L27/0928 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/16 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/517 ,  H01L29/66477 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7841 ,  H01L29/7851 ,  H10B12/00 ,  H10B12/01 ,  H10B12/36 ,  H10B12/056 ,  Y10S257/903

Abstract: A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.

公开(公告)号：US11557667B2

公开(公告)日：2023-01-17

申请号：US16643923

申请日：2017-09-30

Applicant: Intel Corporation

Inventor： Marko Radosavljevic ,  Sansaptak Dasgupta ,  Han Wui Then ,  Ibrahim Ban ,  Paul B. Fischer

IPC: H01L29/778 ,  H01L29/66 ,  H01L21/02 ,  H01L21/306 ,  H01L21/762 ,  H01L29/08 ,  H01L29/20 ,  H01L29/205 ,  H01L29/51

Abstract: A device including a III-N material is described. The device includes a transistor structure having a first layer including a first group III-nitride (III-N) material, a polarization charge inducing layer above the first layer, the polarization charge inducing layer including a second III-N material, a gate electrode above the polarization charge inducing layer and a source structure and a drain structure on opposite sides of the gate electrode. The device further includes a plurality of peripheral structures adjacent to transistor structure, where each of the peripheral structure includes the first layer, but lacks the polarization charge inducing layer, an insulating layer above the peripheral structure and the transistor structure, wherein the insulating layer includes a first dielectric material. A metallization structure, above the peripheral structure, is coupled to the transistor structure.

公开(公告)号：US09664858B2

公开(公告)日：2017-05-30

申请号：US13721965

申请日：2012-12-20

Applicant: Intel Corporation

Inventor： Edris M. Mohammed ,  Peter L. Chang ,  Ibrahim Ban

IPC: G02B6/36 ,  G02B6/122 ,  G02B6/42 ,  G02B6/12 ,  G02B6/132 ,  G02B6/32

CPC classification number: G02B6/36 ,  G02B6/12002 ,  G02B6/12004 ,  G02B6/1228 ,  G02B6/132 ,  G02B6/32 ,  G02B6/4214 ,  G02B2006/12176 ,  G02B2006/12195

Abstract: Systems and methods may couple on-chip optical circuits to external fibers. An SOI waveguide structure may include mirror structures and tapered waveguides to optically couple optical circuits to fibers in a vertically oriented external connector. The mirror structure(s) may be angularly disposed at the ends of the silicon waveguide structure. An oxide layer may cover a buried oxide layer and the silicon waveguide structure. The tapered waveguide(s) may have a narrow end and a wide end. The narrow end of the tapered waveguide(s) may be disposed above the mirror structures. The tapered waveguide(s) may extend through the oxide layer from the narrow end in a direction perpendicular to the silicon waveguide structure. An external connector may fit over the tapered waveguide(s) and uses a fiber array traveling through a connector body to optically couple to the external fiber.

公开(公告)号：US20170207222A1

公开(公告)日：2017-07-20

申请号：US15474689

申请日：2017-03-30

Applicant: Intel Corporation

Inventor： Peter L. D. Chang ,  Uygar E. Avci ,  David Kencke ,  Ibrahim Ban

IPC: H01L27/108 ,  H01L29/51 ,  H01L29/49 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L27/10802 ,  H01L21/28008 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823857 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0924 ,  H01L27/0928 ,  H01L27/108 ,  H01L27/10826 ,  H01L27/10844 ,  H01L27/10879 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/16 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/517 ,  H01L29/66477 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7841 ,  H01L29/785 ,  H01L29/7851 ,  Y10S257/903

Abstract: A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.

公开(公告)号：US20210194459A1

公开(公告)日：2021-06-24

申请号：US16719077

申请日：2019-12-18

Applicant: Intel Corporation

Inventor： Hossein Alavi ,  Ibrahim Ban ,  Telesphor Kamgaing ,  Edris Mohammed ,  Han Wui Then ,  Kevin Obrien ,  Paul Fischer ,  Johanny Escobar Pelaez ,  Ved Gund

IPC: H03H9/54 ,  H03H9/64 ,  H03H9/25 ,  H03H9/58 ,  H03H9/205

Abstract: Techniques are disclosed implementing acoustic wave resonator (AWR) filter architectures to enable integrated solutions requiring significantly less passive components. The primary AWR filter topology leverages the use of parallel resonator branches, each having a relatively narrow bandwidth that may be combined to form an overall broadband filter response. This architecture may be further modified using electronically-controlled switching components to dynamically turn specific branches on or off to tune the filter, thus realizing a programmable broadband solution. Shunt resonators may also be added to the AWR filter topology, which may also be controlled with the use of electronically-controlled switching components to provide further control with respect to roll-off and the location and number of notch frequencies.

公开(公告)号：US10916547B2

公开(公告)日：2021-02-09

申请号：US16900359

申请日：2020-06-12

Applicant: Intel Corporation

Inventor： Peter L. D. Chang ,  Uygar E. Avci ,  David Kencke ,  Ibrahim Ban

IPC: H01L21/00 ,  H01L21/84 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/108 ,  H01L27/12 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28 ,  H01L27/092 ,  H01L29/06 ,  H01L29/49 ,  H01L29/51 ,  H01L29/16

Abstract: A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.

公开(公告)号：US09786667B2

公开(公告)日：2017-10-10

申请号：US15474689

申请日：2017-03-30

Applicant: Intel Corporation

Inventor： Peter L. D. Chang ,  Uygar E. Avci ,  David Kencke ,  Ibrahim Ban

IPC: H01L21/00 ,  H01L21/84 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/108 ,  H01L29/78 ,  H01L29/06 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L27/10802 ,  H01L21/28008 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823857 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0924 ,  H01L27/0928 ,  H01L27/108 ,  H01L27/10826 ,  H01L27/10844 ,  H01L27/10879 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/16 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/517 ,  H01L29/66477 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7841 ,  H01L29/785 ,  H01L29/7851 ,  Y10S257/903

Abstract: A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.

公开(公告)号：US11462540B2

公开(公告)日：2022-10-04

申请号：US17142176

申请日：2021-01-05

Applicant: Intel Corporation

Inventor： Peter L. D. Chang ,  Uygar E. Avci ,  David Kencke ,  Ibrahim Ban

IPC: H01L21/00 ,  H01L21/84 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/108 ,  H01L27/12 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28 ,  H01L27/092 ,  H01L29/06 ,  H01L29/49 ,  H01L29/51 ,  H01L29/16

Abstract: A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.

公开(公告)号：US11335777B2

公开(公告)日：2022-05-17

申请号：US16629551

申请日：2017-08-09

Applicant: Intel Corporation

Inventor： Kevin L. Lin ,  Paul B. Fischer ,  Han Wui Then ,  Sansaptak Dasgupta ,  Marko Radosavljevic ,  Ibrahim Ban

IPC: H01L29/10 ,  H01L21/764 ,  H01L27/12 ,  H01L21/3065 ,  H01L21/762 ,  H01L21/84 ,  H01L23/522 ,  H01L23/528 ,  H01L29/20 ,  H01L29/205 ,  H01L29/423 ,  H01L29/778

Abstract: Disclosed herein are integrated circuit (IC) components with substrate cavities, as well as related techniques and assemblies. In some embodiments, an IC component may include a substrate, a device layer on the substrate, a plurality of interconnect layers on the device layer, and a cavity in the substrate.

公开(公告)号：US10720434B2

公开(公告)日：2020-07-21

申请号：US16452469

申请日：2019-06-25

Applicant: Intel Corporation

Inventor： Peter L. D. Chang ,  Uygar E. Avci ,  David Kencke ,  Ibrahim Ban

IPC: H01L21/00 ,  H01L21/84 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/108 ,  H01L27/12 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28 ,  H01L27/092 ,  H01L29/06 ,  H01L29/49 ,  H01L29/51 ,  H01L29/16

Abstract: A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.