公开(公告)号：US20220116044A1

公开(公告)日：2022-04-14

申请号：US17556917

申请日：2021-12-20

Applicant: Intel Corporation

Inventor： Sharath Raghava ,  Ankireddy Nalamalpu ,  Dheeraj Subbareddy ,  Harsha Gupta ,  James Ball ,  Kavitha Prasad ,  Sean R. Atsatt

IPC: H03K19/17736 ,  H03K19/17796 ,  H04L41/5019

Abstract: Techniques described herein may relate to providing a programmable interconnect network (e.g., a programmable network-on-chip (NOC)). A method may include determining a transmission parameter, bonding one or more channels of an interconnect network based at least in part on the transmission parameter, and power-gating any unused channels after the bonding.

公开(公告)号：US11223361B2

公开(公告)日：2022-01-11

申请号：US16882029

申请日：2020-05-22

Applicant: Intel Corporation

Inventor： Kevin Clark ,  Scott J. Weber ,  James Ball ,  Simon Chong ,  Ravi Prakash Gutala ,  Aravind Raghavendra Dasu ,  Jun Pin Tan

IPC: H03K19/1776 ,  H03K19/17704 ,  H03K19/17758 ,  H03K19/17768

Abstract: An integrated circuit device may include programmable logic fabric disposed on a first integrated circuit die and having configuration memory. The integrated circuit device may also include a base die that may provide memory and/or operating supporting circuitry. The first die and the second die may be coupled using a high-speed parallel interface. The interface may employ microbumps. The first die and the second die may also include controllers for the interface.

公开(公告)号：US11206024B2

公开(公告)日：2021-12-21

申请号：US17033524

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Sharath Raghava ,  Ankireddy Nalamalpu ,  Dheeraj Subbareddy ,  Harsha Gupta ,  James Ball ,  Kavitha Prasad ,  Sean R. Atsatt

IPC: H03K19/177 ,  H03K19/17736 ,  H03K19/17796 ,  H04L12/24

Abstract: Techniques described herein may relate to providing a programmable interconnect network (e.g., a programmable network-on-chip (NOC)). A method may include determining a transmission parameter, bonding one or more channels of an interconnect network based at least in part on the transmission parameter, and power-gating any unused channels after the bonding.

公开(公告)号：US20210058085A1

公开(公告)日：2021-02-25

申请号：US17094612

申请日：2020-11-10

Applicant: Intel Corporation

Inventor： Kevin Clark ,  Scott J. Weber ,  James Ball ,  Ravi Prakash Gutala ,  Aravind Raghavendra Dasu

IPC: H03K19/1776 ,  G11C7/10 ,  H01L25/065 ,  G11C5/02

Abstract: An integrated circuit device may include a programmable fabric die having programmable logic fabric and configuration memory that may configure the programmable logic fabric. The integrated circuit device may also include a base die that may provide fabric support circuitry, including memory and/or communication interfaces. The first die and the second die may be coupled using a multi-purpose interface that may allow communication between the first die and the second die. The multi-purpose interface may allow concurrent access to the base die by the programmable logic fabric and the configuration memory by using multiple channels over the multi-purpose interface.

公开(公告)号：US10833679B2

公开(公告)日：2020-11-10

申请号：US16235984

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Kevin Clark ,  Scott J. Weber ,  James Ball ,  Ravi Prakash Gutala ,  Aravind Raghavendra Dasu

IPC: H03K19/177 ,  H01L25/00 ,  H03K19/1776 ,  G11C7/10 ,  H01L25/065 ,  G11C5/02

Abstract: An integrated circuit device may include a programmable fabric die having programmable logic fabric and configuration memory that may configure the programmable logic fabric. The integrated circuit device may also include a base die that may provide fabric support circuitry, including memory and/or communication interfaces. The first die and the second die may be coupled using a multi-purpose interface that may allow communication between the first die and the second die. The multi-purpose interface may allow concurrent access to the base die by the programmable logic fabric and the configuration memory by using multiple channels over the multi-purpose interface.

公开(公告)号：US20190103872A1

公开(公告)日：2019-04-04

申请号：US16146849

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Kevin Clark ,  Scott J. Weber ,  James Ball ,  Simon Chong ,  Ravi Prakash Gutala ,  Aravind Raghavendra Dasu

IPC: H03K19/177

Abstract: An integrated circuit device may include programmable logic fabric disposed on a first integrated circuit die and having configuration memory. The integrated circuit device may also include a base die that may provide memory and/or operating supporting circuitry. The first die and the second die may be coupled using a high-speed parallel interface. The interface may employ microbumps. The first die and the second die may also include controllers for the interface.

公开(公告)号：US20230370068A1

公开(公告)日：2023-11-16

申请号：US18198122

申请日：2023-05-16

Applicant: Intel Corporation

Inventor： Sharath Raghava ,  Ankireddy Nalamalpu ,  Dheeraj Subbareddy ,  Harsha Gupta ,  James Ball ,  Kavitha Prasad ,  Sean R. Atsatt

IPC: H03K19/17736 ,  H03K19/17796 ,  H04L41/5019

CPC classification number: H03K19/17736 ,  H03K19/17796 ,  H04L41/5019 ,  H04L41/5003

Abstract: Techniques described herein may relate to providing a programmable interconnect network (e.g., a programmable network-on-chip (NOC)). A method may include determining a transmission parameter, bonding one or more channels of an interconnect network based at least in part on the transmission parameter, and power-gating any unused channels after the bonding.

公开(公告)号：US10790827B2

公开(公告)日：2020-09-29

申请号：US16234212

申请日：2018-12-27

Applicant: Intel Corporation

Inventor： Sharath Raghava ,  Ankireddy Nalamalpu ,  Dheeraj Subbareddy ,  Harsha Gupta ,  James Ball ,  Kavitha Prasad ,  Sean R. Atsatt

IPC: H04L12/28 ,  H03K19/17736 ,  H03K19/17796 ,  H04L12/24

Abstract: Techniques described herein may relate to providing a programmable interconnect network (e.g., a programmable network-on-chip (NOC)). A method may include determining a transmission parameter, bonding one or more channels of an interconnect network based at least in part on the transmission parameter, and power-gating any unused channels after the bonding.

公开(公告)号：US20190131975A1

公开(公告)日：2019-05-02

申请号：US16234212

申请日：2018-12-27

Applicant: Intel Corporation

Inventor： Sharath Raghava ,  Ankireddy Nalamalpu ,  Dheeraj Subbareddy ,  Harsha Gupta ,  James Ball ,  Kavitha Prasad ,  Sean R. Atsatt

IPC: H03K19/177

CPC classification number: H03K19/17736 ,  H03K19/17796 ,  H04L41/5003 ,  H04L41/5019

Abstract: Techniques described herein may relate to providing a programmable interconnect network (e.g., a programmable network-on-chip (NOC)). A method may include determining a transmission parameter, bonding one or more channels of an interconnect network based at least in part on the transmission parameter, and power-gating any unused channels after the bonding.