公开(公告)号：US10884735B2

公开(公告)日：2021-01-05

申请号：US15905623

申请日：2018-02-26

Applicant: Intel Corporation

Inventor： Jayesh Iyer ,  Jamison Collins ,  Sebastian Winkel ,  Howard Chen

IPC: G06F9/30

Abstract: A processor includes a front end to receive an instruction. The processor also includes a core to execute the instruction. The core includes logic to execute a base function of the instruction to yield a result, generate a predicate value of a comparison of the result based upon a predication setting in the instruction, and set the predicate value in a register. The processor also includes a retirement unit to retire the instruction.

公开(公告)号：US10324724B2

公开(公告)日：2019-06-18

申请号：US14971904

申请日：2015-12-16

Applicant: Intel Corporation

Inventor： Patrick P. Lai ,  Tyler N. Sondag ,  Sebastian Winkel ,  Polychronis Xekalakis ,  Ethan Schuchman ,  Jayesh Iyer

IPC: G06F9/30

Abstract: Methods and apparatuses relating to a fusion manager to fuse instructions are described. In one embodiment, a hardware processor includes a hardware binary translator to translate an instruction stream into a translated instruction stream, a hardware fusion manager to fuse multiple instructions of the translated instruction stream into a single fused instruction, a hardware decode unit to decode the single fused instruction into a decoded, single fused instruction, and a hardware execution unit to execute the decoded, single fused instruction.

公开(公告)号：US10241789B2

公开(公告)日：2019-03-26

申请号：US15391789

申请日：2016-12-27

Applicant: Intel Corporation

Inventor： Alexander Y. Ostanevich ,  Sergey P. Scherbinin ,  Jayesh Iyer ,  Dmitry M. Maslennikov ,  Denis G. Motin ,  Alexander V. Ermolovich ,  Andrey Chudnovets ,  Sergey A. Rozhkov ,  Boris A. Babayan

IPC: G06F9/312 ,  G06F9/40 ,  G06F9/30 ,  G06F9/38

Abstract: An apparatus includes a binary translator to hoist a load instruction in a branch of a conditional statement above the conditional statement and insert a speculation control of load (SCL) instruction in a complementary branch of the conditional statement, where the SCL instruction provides an indication of a real program order (RPO) of the load instruction before the load instruction was hoisted. The apparatus further includes an execution circuit to execute the load instruction to perform a load and cause an entry for the load instruction to be inserted in an ordering buffer, and where the execution circuit is to execute the SCL instruction to locate the entry for the load instruction in the ordering buffer using the RPO of the load instruction provided by the SCL instruction and discard the entry for the load instruction from the ordering buffer.

公开(公告)号：US10235171B2

公开(公告)日：2019-03-19

申请号：US15391791

申请日：2016-12-27

Applicant: Intel Corporation

Inventor： Alexander Y. Ostanevich ,  Jayesh Iyer ,  Sergey P. Scherbinin ,  Dmitry M. Maslennikov ,  Denis G. Motin ,  Alexander V. Ermolovich ,  Andrey Chudnovets ,  Sergey A. Rozhkov ,  Boris A. Babayan

IPC: G06F9/38 ,  G06F9/30

Abstract: An apparatus includes a first circuit to determine a real program order (RPO) of an eldest undispatched instruction from among a plurality of strands, a second circuit to determine an RPO limit based on a delta value and the RPO of the eldest undispatched instruction, an ordering buffer to store entries for instructions that are waiting to be retired, and a third circuit to execute an orderable instruction from a strand from the plurality of strands to cause an entry for the orderable instruction to be inserted into the ordering buffer in response to a determination that an RPO of the orderable instruction is less than or equal to the RPO limit.

公开(公告)号：US20190042247A1

公开(公告)日：2019-02-07

申请号：US15905623

申请日：2018-02-26

Applicant: Intel Corporation

Inventor： Jayesh Iyer ,  Jamison Collins ,  Sebastian Winkel ,  Howard Chen

IPC: G06F9/30

Abstract: A processor includes a front end to receive an instruction. The processor also includes a core to execute the instruction. The core includes logic to execute a base function of the instruction to yield a result, generate a predicate value of a comparison of the result based upon a predication setting in the instruction, and set the predicate value in a register. The processor also includes a retirement unit to retire the instruction.

公开(公告)号：US10095623B2

公开(公告)日：2018-10-09

申请号：US15297084

申请日：2016-10-18

Applicant: Intel Corporation

Inventor： Andrey Kluchnikov ,  Jayesh Iyer ,  Sergey Y. Shishlov ,  Boris A. Babayan

IPC: G06F12/00 ,  G06F12/0844 ,  G06F12/0875 ,  G06F3/06 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0842 ,  G06F13/18 ,  G06F9/52

Abstract: Methods and apparatuses to control access to a multiple bank data cache are described. In one embodiment, a processor includes conflict resolution logic to detect multiple instructions scheduled to access a same bank of a multiple bank data cache in a same clock cycle and to grant access priority to an instruction of the multiple instructions scheduled to access a highest total of banks of the multiple bank data cache. In another embodiment, a method includes detecting multiple instructions scheduled to access a same bank of a multiple bank data cache in a same clock cycle, and granting access priority to an instruction of the multiple instructions scheduled to access a highest total of banks of the multiple bank data cache.

公开(公告)号：US20180181398A1

公开(公告)日：2018-06-28

申请号：US15392626

申请日：2016-12-28

Applicant: Intel Corporation

Inventor： Sergey P. Scherbinin ,  Jayesh Iyer ,  Alexander Y. Ostanevich ,  Dmitry Maslennikov ,  Denis G. Motin ,  Alexander V. Ermolovich ,  Andrey Chudnovets ,  Sergey A. Rozhkov ,  Boris A. Babayan

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/35

CPC classification number: G06F9/30083 ,  G06F8/452 ,  G06F9/3004 ,  G06F9/30072 ,  G06F9/30145 ,  G06F9/3017 ,  G06F9/325 ,  G06F9/35 ,  G06F9/3802 ,  G06F9/3851 ,  G06F9/3867 ,  G06F9/3885

Abstract: Embodiments described herein relate to apparatus and methods for decomposing loops to improve performance and power efficiency. In one embodiment, a processor includes: a loop accelerator including a plurality of strand execution circuits, a binary translator to: receive a plurality of instructions from an instruction storage, to determine whether the plurality of instructions include loop instructions, and, in response to determining that they do, to divide the loop instructions into two or more jobs using at least one job creation rule, to assign the two or more jobs to two or more strands using at least one strand creation rule, and to cause the loop accelerator to execute at least two of the two or more strands in parallel using the plurality of strand execution circuits.

公开(公告)号：US09632790B2

公开(公告)日：2017-04-25

申请号：US13993794

申请日：2012-12-26

Applicant: Intel Corporation

Inventor： Jayesh Iyer ,  Nikolay Kosarev ,  Sergey Y. Shishlov ,  Alexey Y. Sivtsov ,  Yuriy V Baida ,  Alexander V Butuzov ,  Bob Babayan ,  Vladimir Pentkovski

IPC: G06F9/38

CPC classification number: G06F9/3836 ,  G06F9/3851 ,  G06F9/3855

Abstract: A processing device comprises select logic to schedule a plurality of instructions for execution. The select logic calculates a reconstructed program order (RPO) value for each of a plurality of instructions that are ready to be scheduled for execution. The select logic creates an ordered list of instructions based on the delayed RPO values, the delayed RPO values comprising the calculated RPO values from a previous execution cycle, and dispatches instructions for scheduling based on the ordered list.

公开(公告)号：US20160328239A1

公开(公告)日：2016-11-10

申请号：US14704108

申请日：2015-05-05

Applicant: Intel Corporation

Inventor： Jayesh Iyer ,  Jamison D. Collins ,  Sebastian Winkel

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/384 ,  G06F9/30112 ,  G06F11/1056

Abstract: In one embodiment, a processor includes logic, responsive to a first instruction, to perform an operation on a first source operand and a second source operand associated with the first instruction and write a result of the operation to a destination location comprising a third source operand. The write may be a partial write of the destination location to maintain an unmodified portion of the third source operand. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括响应于第一指令的逻辑，以对与第一指令相关联的第一源操作数和第二源操作数执行操作，并将操作的结果写入到包括第三源操作数的目的位置 。 写入可以是目的地位置的部分写入，以维持第三源操作数的未修改部分。 描述和要求保护其他实施例。

公开(公告)号：US20160092367A1

公开(公告)日：2016-03-31

申请号：US14498902

申请日：2014-09-26

Applicant: INTEL CORPORATION

Inventor： Andrey Kluchnikov ,  Jayesh Iyer ,  Sergey Y. Shishlov ,  Boris A. Babayan

IPC: G06F12/08

CPC classification number: G06F12/0844 ,  G06F3/0613 ,  G06F3/0637 ,  G06F3/0659 ,  G06F3/0673 ,  G06F9/52 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0875 ,  G06F13/18 ,  G06F2212/1008 ,  G06F2212/1016 ,  G06F2212/251 ,  G06F2212/452

Abstract: Methods and apparatuses to control access to a multiple bank data cache are described. In one embodiment, a processor includes conflict resolution logic to detect multiple instructions scheduled to access a same bank of a multiple bank data cache in a same clock cycle and to grant access priority to an instruction of the multiple instructions scheduled to access a highest total of banks of the multiple bank data cache. In another embodiment, a method includes detecting multiple instructions scheduled to access a same bank of a multiple bank data cache in a same clock cycle, and granting access priority to an instruction of the multiple instructions scheduled to access a highest total of banks of the multiple bank data cache.

Abstract translation: 描述了控制对多存储体数据缓存的访问的方法和装置。 在一个实施例中，处理器包括冲突解决逻辑，以检测被调度以在相同时钟周期内访问多存储体数据高速缓存的相同存储体的多个指令，并且为预定访问最高总数的多个指令的指令授予访问优先级 银行多银行数据缓存。 在另一个实施例中，一种方法包括检测被调度以在相同时钟周期内访问多存储体数据高速缓存的同一个存储体的多个指令，以及授予被调度以访问该多个存储体中多个存储体的最高总数组的多个指令的指令的访问优先级 银行数据缓存。