公开(公告)号：US20240006376A1

公开(公告)日：2024-01-04

申请号：US17857062

申请日：2022-07-04

Applicant: Intel Corporation

Inventor： Seok Ling LIM ,  Jenny Shio Yin ONG ,  Bok Eng CHEAH ,  Jackson Chung Peng KONG ,  Kooi Chi OOI

IPC: H01L25/065 ,  H01L25/18 ,  H01L25/00

CPC classification number: H01L25/0652 ,  H01L25/18 ,  H01L25/50 ,  H01L2225/06582 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2225/06513

Abstract: A semiconductor package includes a silicon die including a first die surface coupled to a package substrate, a second die surface opposite to the first die surface, and at least one die sidewall orthogonal to the first die surface and the second die surface, and a mold layer including a first mold surface, a second mold surface opposite to the first mold surface, and at least one mold sidewall orthogonal to the first mold surface and the second mold surface, the at least one mold sidewall being disposed along the at least one die sidewall, and the mold layer further including a power conductive corridor extending from the first mold surface and coupled to the package substrate through the first mold surface. The semiconductor package further includes a first stacked device coupled to the first die surface and to the power conductive corridor through the first mold surface.

公开(公告)号：US20230187368A1

公开(公告)日：2023-06-15

申请号：US17548628

申请日：2021-12-13

Applicant: Intel Corporation

Inventor： Seok Ling LIM ,  Bok Eng CHEAH ,  Jenny Shio Yin ONG ,  Jackson Chung Peng KONG ,  Kooi Chi OOI

IPC: H01L23/538 ,  H01L23/13 ,  H01L21/48

CPC classification number: H01L23/5386 ,  H01L23/13 ,  H01L23/5383 ,  H01L23/5385 ,  H01L21/4857

Abstract: The present disclosure generally relates to an electronic assembly. The electronic assembly may include a first substrate including a first surface, an opposing second surface and a recess opening extending through the first surface. The electronic assembly may also include a power delivery mold frame including a first mold surface, an opposing second mold surface, a plurality of first metal planes and a plurality of second metal planes extending between the first and second mold surfaces, the power delivery mold frame arranged in the recess opening and coupled to the first substrate through the first mold surface. The electronic assembly may further include a second substrate including a subsequent first surface, an opposing subsequent second surface, the second substrate coupled to the power delivery mold frame through a plurality of first solder bumps and further coupled to the first substrate through a plurality of second solder bumps at the subsequent first surface.

公开(公告)号：US20230065380A1

公开(公告)日：2023-03-02

申请号：US17411062

申请日：2021-08-25

Applicant: Intel Corporation

Inventor： Bok Eng CHEAH ,  Seok Ling LIM ,  Jenny Shio Yin ONG ,  Jackson Chung Peng KONG ,  Kooi Chi OOI

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48 ,  H01L25/00

Abstract: The present disclosure is directed to multichip semiconductor packages, and methods for making them, which includes a package substrate with an integrated bridge frame having a first horizontal portion positioned on a top surface of the package substrate, with first and second dies positioned overlapping the first horizontal portion of the bridge frame, and a second horizontal portion positioned on the bottom surface of the package substrate, with third and fourth dies positioned overlapping the second horizontal portion of the bridge frame. The bridge frame further includes first and second vertical portions separated by a portion of the package substrate positioned under the first horizontal portion of the bridge frame between the top surface and bottom surfaces of the package substrate, and a plurality of vertical interconnects adjacent to the first and second vertical portions of the bridge frame.

公开(公告)号：US20220071022A1

公开(公告)日：2022-03-03

申请号：US17089748

申请日：2020-11-05

Applicant: Intel Corporation

Inventor： Jackson Chung Peng KONG ,  Bok Eng CHEAH ,  Jenny Shio Yin ONG ,  Seok Ling LIM

IPC: H05K3/34 ,  H05K1/18

Abstract: According to various examples, a device is described. The device may include a printed circuit board. The device may also include a first recess in the printed circuit board, wherein the first recess comprises a circular side surface and a bottom surface. The device may also include a first solder ball disposed in the first recess. The device may also include a first conductive wall positioned behind the circular side surface of the first recess, wherein the first conductive wall surrounds a side surface of the first solder ball.

公开(公告)号：US20220068846A1

公开(公告)日：2022-03-03

申请号：US17087667

申请日：2020-11-03

Applicant: Intel Corporation

Inventor： Jenny Shio Yin ONG ,  Bok Eng CHEAH ,  Jackson Chung Peng KONG ,  Seok Ling LIM ,  Kooi Chi OOI

IPC: H01L23/64 ,  H01L23/498 ,  H01L23/48 ,  H01L21/48 ,  H01G4/224 ,  H01L23/00 ,  H01L25/18

Abstract: The present disclosure relates to a semiconductor package, that may include a package substrate, a base die arranged on and electrically coupled to the package substrate, and at least one power plane module arranged on the package substrate at a periphery of the base die. The power plane module may include a top surface and a bottom surface, and at least one vertical interleaving metal layer electrically coupled at the bottom surface to the package substrate. The semiconductor package may further include a semiconductor device including a first section disposed on the base die, and a second section disposed on the power plane module, wherein the second section of the semiconductor device may be electrically coupled to the at least one vertical interleaving metal layer at the top surface of the power plane module.

公开(公告)号：US20180366423A1

公开(公告)日：2018-12-20

申请号：US15977617

申请日：2018-05-11

Applicant: Intel Corporation

Inventor： Jenny Shio Yin ONG ,  Bok Eng CHEAH ,  Jackson Chung Peng KONG ,  Seok Ling LIM

IPC: H01L23/64 ,  H01L23/538 ,  H01L23/498 ,  H01L23/552

CPC classification number: H01L23/645 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/552 ,  H01L23/642 ,  H01L2224/16225 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/19106

Abstract: Embodiments of the present disclosure provide a semiconductor package configured to provide for a disposition of one or more package components on a substrate within a footprint of a package die. In embodiments, the package may include a package substrate having a first side and a second side opposite the first side. An area of the first side of the package substrate within which a die is to be disposed may form a footprint of the die on the substrate. The package may further include a voltage reference plane coupled with the second side of the package substrate. At least a portion of the voltage reference plane may be disposed within the die footprint, to provide a reference voltage to components to be disposed within the footprint on the second side of the substrate, and to shield these components from electromagnetic interference. Other embodiments may be described and/or claimed.

公开(公告)号：US20240006341A1

公开(公告)日：2024-01-04

申请号：US17857059

申请日：2022-07-04

Applicant: Intel Corporation

Inventor： Bok Eng CHEAH ,  Seok Ling LIM ,  Jenny Shio Yin ONG ,  Jackson Chung Peng KONG ,  Kooi Chi OOI

IPC: H01L23/00 ,  H01L23/498 ,  H01L25/18 ,  H01L21/48

CPC classification number: H01L23/562 ,  H01L23/49822 ,  H01L25/18 ,  H01L24/16 ,  H01L21/4803 ,  H01L2224/16225

Abstract: A semiconductor package including: a package substrate including a base die disposed on a top surface of the package substrate, the base die including a plurality of electrical components disposed on a top surface of the base die, the plurality of electrical components including a first electrical component configured adjacent to a second electrical component, wherein the first electrical component and the second electrical component have an asymmetric form-factor; and a stiffener including: a stiffener main portion, wherein the stiffener main portion is affixed to the top surface of the package substrate and configured at least partially surrounding the base die; and a stiffener extension portion configured to extend from the stiffener main portion to be disposed at least partially over the top surface of the base die adjacent to the first electrical component and the second electrical component.

公开(公告)号：US20230411385A1

公开(公告)日：2023-12-21

申请号：US18242322

申请日：2023-09-05

Applicant: Intel Corporation

Inventor： Seok Ling LIM ,  Jenny Shio Yin ONG ,  Tin Poay CHUAH ,  Hon Wah CHEW

IPC: H01L27/08 ,  H01L23/522 ,  H01L23/498 ,  H01L23/64

CPC classification number: H01L27/0805 ,  H01L28/40 ,  H01L23/5223 ,  H01L23/49822 ,  H01L23/642 ,  H01L23/50

Abstract: An apparatus is provided which comprises: one or more dielectric layers forming a substrate, one or more first conductive contacts on a top surface of the substrate, one or more second conductive contacts on a bottom surface of the substrate opposite of the top surface, and one or more discrete capacitors conductively coupled with one or more of the first and second conductive contacts, the one or more discrete capacitors embedded within the substrate between the top surface and the bottom surface. Other embodiments are also disclosed and claimed.

公开(公告)号：US20230120513A1

公开(公告)日：2023-04-20

申请号：US17971442

申请日：2022-10-21

Applicant: Intel Corporation

Inventor： Jackson Chung Peng KONG ,  Bok Eng CHEAH ,  Seok Ling LIM ,  Kooi Chi OOI ,  Jenny Shio Yin ONG

IPC: H05K1/11

Abstract: Foldable Compression Attached Memory Modules (fCAMMs) and associated apparatus, assemblies and systems. The fCAMM comprises a compression contact module having a plurality of contact means arranged in one or more arrays on its underside, first and second fold modules including multiple memory devices, and flexible interconnects coupling the compression contact module to the first and second fold modules. Under one assembled configuration, portions of printed circuit boards (PCBs) for the first and second fold modules are folded over portions of the compression contact module. Under another configuration, the first fold module is disposed above the second fold module, which is disposed above the compression contact module. In an assembly or system including a motherboard, a compression mount technology (CMT) connector or a land grid array (LGA) assembly is disposed between the motherboard and the compression contact module. Bolster plates are used to urge the compression contact module toward the motherboard.

公开(公告)号：US20220077060A1

公开(公告)日：2022-03-10

申请号：US17089745

申请日：2020-11-05

Applicant: Intel Corporation

Inventor： Seok Ling LIM ,  Bok Eng CHEAH ,  Jenny Shio Yin ONG ,  Jackson Chung Peng KONG

IPC: H01L23/528 ,  H01L21/768 ,  H01L21/56 ,  H01L25/065 ,  H01L23/31 ,  H01L23/538 ,  H01L23/50

Abstract: A semiconductor package including a molded power delivery module arranged between a package substrate and a semiconductor chip and including a plurality of input conductive structures and a plurality of reference conductive structures, wherein the input conductive structures alternate between the plurality of reference conductive structures, wherein the input conductive structure is electrically coupled with a chip input voltage terminal and a package input voltage terminal, wherein each of the plurality of reference conductive structures are electrically coupled with a semiconductor chip reference terminal and a package reference terminal.