公开(公告)号：US20190355700A1

公开(公告)日：2019-11-21

申请号：US16474016

申请日：2016-12-28

Applicant: Intel Corporation

Inventor： Aiping Tan ,  Bin Liu ,  Li Deng ,  Yong She ,  Zhicheng Ding ,  Mao Guo

IPC: H01L25/065 ,  H01L25/00 ,  H01L21/56 ,  H01L23/31

Abstract: Techniques for providing an integrated circuit package that avoids or eliminates x-y area and z-height compared to conventional integrated circuit packages. In certain examples, an example package can utilize a substrate with an opening and bottom side or sidewall terminations to avoid adding addition x-y substrate area or z-axis package height associated with an integrated circuit die of a stack of integrated circuit dies of the package.

公开(公告)号：US20180204821A1

公开(公告)日：2018-07-19

申请号：US15755219

申请日：2015-09-23

Applicant: Intel Corporation

Inventor： Mao Guo ,  Min-Tih Lai ,  Tyler Charles Leuten

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48 ,  H01L25/00

Abstract: Substrates, assemblies, and techniques for enabling multi-chip flip chip packages are disclosed herein. For example, in some embodiments, a package substrate may include a first side face; a second side face, wherein the second side face is opposite to the first side face along an axis; a portion of insulating material extending from the first side face to the second side face; wherein a cross-section of the portion of insulating material taken perpendicular to the axis has a stairstep profile. Solder pads may be disposed at base and step surfaces of the portion of insulating material. One or more dies may be coupled to the package substrate (e.g., to form a multi-chip flip chip package), and in some embodiments, additional IC packages may be coupled to the package substrate. In some embodiments, the package substrate may be reciprocally symmetric or approximately reciprocally symmetric.

公开(公告)号：US09859255B1

公开(公告)日：2018-01-02

申请号：US15283342

申请日：2016-10-01

Applicant: Intel Corporation

Inventor： Jh Yoon ,  Yong She ,  Mao Guo ,  Richard Patten

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/00 ,  H01L23/29 ,  H01L25/18 ,  H01L21/56 ,  H01L25/00 ,  H01L21/768

CPC classification number: H01L25/0657 ,  H01L21/565 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/293 ,  H01L23/3128 ,  H01L23/49833 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/81 ,  H01L24/85 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0231 ,  H01L2224/0237 ,  H01L2224/0239 ,  H01L2224/13024 ,  H01L2224/13147 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06551 ,  H01L2225/06558 ,  H01L2225/06572 ,  H01L2225/06575 ,  H01L2225/06586 ,  H01L2924/0665 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/15311

Abstract: Electronic device package technology is disclosed. An electronic device package in accordance with the present disclosure can include a package substrate, an electronic component, a mold compound encapsulating the electronic component, and a redistribution layer disposed such that the mold compound is between the package substrate and the redistribution layer. The redistribution layer and the package substrate can be electrically coupled. In addition, the redistribution layer and the electronic component can be electrically coupled to electrically couple the electronic component and the package substrate. Associated systems and methods are also disclosed.