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    Analog-to-digital converter system, transceiver, base station and mobile device
    12.
    发明授权
    Analog-to-digital converter system, transceiver, base station and mobile device 有权

    公开(公告)号：US11528182B2

    公开(公告)日：2022-12-13

    申请号：US17351288

    申请日：2021-06-18

    Applicant: Intel Corporation

    Inventor： Kameran Azadet ,  Martin Clara ,  Daniel Gruber ,  Christian Lindholm ,  Hundo Shin

    IPC: H03M1/10 ,  H04L27/36 ,  H03M1/06 ,  H04B1/04

    Abstract: An Analog-to-Digital Converter, ADC, system is provided. The ADC system comprises a plurality of ADC circuits and a first input for receiving a transmit signal of a transceiver. One ADC circuit of the plurality of ADC circuits is coupled to the first input and configured to provide first digital data based on the transmit signal. The ADC system further comprises a second input for receiving a receive signal of the transceiver. The other ADC circuits of the plurality of ADC circuits are coupled to the second input, wherein the other ADC circuits of the plurality of ADC circuits are time-interleaved and configured to provide second digital data based on the receive signal. Additionally, the ADC system comprises a first output configured to output digital feedback data based on the first digital data, and a second output configured to output digital receive data based on the second digital data.

    Apparatus and method for analog-to-digital conversion
    13.
    发明授权
    Apparatus and method for analog-to-digital conversion 有权

    公开(公告)号：US11038516B1

    公开(公告)日：2021-06-15

    申请号：US16886817

    申请日：2020-05-29

    Applicant: Intel Corporation

    Inventor： Kameran Azadet ,  Ramon Sanchez ,  Albert Molina ,  Martin Clara ,  Daniel Gruber ,  Matteo Camponeschi

    IPC: H03M1/10 ,  H03M1/34 ,  H03M1/06

    Abstract: An apparatus and method for analog-to-digital conversion. The apparatus includes a first analog-to-digital converter (ADC), a second ADC, and a calibration unit. The first ADC is configured to sample an input analog signal at a first sampling frequency. The second ADC is configured to sample the input analog signal at a second sampling frequency. The second sampling frequency is a fraction of the first sampling frequency. The calibration unit is configured to correct a distortion incurred in an output of the first ADC based on an output of the second ADC. The first ADC may be a time-interleaved ADC. The second ADC may be an extra sub-ADC of the time-interleaved ADC. The second ADC may be configured to sample the input analog signal at random sampling phases. A dithering noise may be added to the input analog signal of the second ADC. The calibration unit may be a non-linear equalizer.

    Digital-to-analog converter and method for correcting gain mismatch between a first segment and a second segment of a digital-to-analog converter
    14.
    发明授权
    Digital-to-analog converter and method for correcting gain mismatch between a first segment and a second segment of a digital-to-analog converter 有权

    公开(公告)号：US10090854B1

    公开(公告)日：2018-10-02

    申请号：US15704152

    申请日：2017-09-14

    Applicant: Intel Corporation

    Inventor： Martin Clara

    IPC: H03M1/66 ,  H03M1/68 ,  H03M1/08 ,  H03M1/10 ,  H03M1/70

    Abstract: A method for correcting gain mismatch between a first segment and a second segment of a digital-to-analog converter is provided. The first segment generates a first contribution to an analog output signal of the digital-to-analog converter based on a first number of bits of a digital input word for the digital-to-analog converter, wherein the second segment generates a second contribution to the analog output signal based on a second number of bits of the digital input word. The method includes extending a numeric range of a second control word for the second segment by a predefined number of bits, wherein the second control word is indicative of the second number of bits. Further, the method includes multiplying the second control word by a correction value that is based on information about a gain error of the first segment. The method additionally includes digitally filtering the multiplied first control word. After the digital filtering, the method further includes reducing the numeric range of the multiplied second control word by the predefined number of bits to generate a modified second control word for the second segment. Additionally, the method includes supplying the modified second control word as input to the second segment.

    Circuitry for digital-to-analog conversion, differential systems and digital-to-analog converter
    16.
    发明授权
    Circuitry for digital-to-analog conversion, differential systems and digital-to-analog converter 有权

    公开(公告)号：US12261622B2

    公开(公告)日：2025-03-25

    申请号：US17358152

    申请日：2021-06-25

    Applicant: Intel Corporation

    Inventor： Michael Kalcher ,  Daniel Gruber ,  Martin Clara

    IPC: H03M1/78 ,  H03M1/80

    Abstract: Circuitry for digital-to-analog conversion is provided. The circuitry includes a driver circuit and a weighting resistor circuit coupled to an output of the driver circuit. The weighting resistor circuit includes a first resistive sub-circuit coupled to the output of the driver circuit and an intermediate node. The weighting resistor further includes a second resistive sub-circuit coupled to the intermediate node and a common node. Further, the weighting circuit includes a third resistive sub-circuit coupled to the intermediate node and an output of the circuitry. The resistivity of the second resistive sub-circuit is equal to or smaller than the resistivity of the first resistive sub-circuit.

    Apparatus and method for time-interleaved analog-to-digital conversion
    18.
    发明授权
    Apparatus and method for time-interleaved analog-to-digital conversion 有权

    公开(公告)号：US11082054B1

    公开(公告)日：2021-08-03

    申请号：US16912812

    申请日：2020-06-26

    Applicant: Intel Corporation

    Inventor： Giacomo Cascio ,  Christian Lindholm ,  Albert Molina ,  Martin Clara

    IPC: H03M1/12 ,  H03M1/06 ,  H03M1/36

    Abstract: The present disclosure relates to a time-interleaved ADC circuit. The time-interleaved ADC circuit comprises an input for an analog input signal, a first ADC bank comprising a first plurality of parallel time-multiplexed ADCs, wherein the first plurality of parallel time-multiplexed ADCs is configured to subsequently generate a first plurality of samples of the analog input signal during a first time interval, a first buffer amplifier coupled between the input and the first ADC bank. The time-interleaved ADC circuit further comprises a second ADC bank comprising a second plurality of parallel time-multiplexed ADCs, wherein the second plurality of parallel time-multiplexed ADCs is configured to subsequently generate a second plurality of samples of the analog input signal during a second time interval, wherein the first and the second time intervals are subsequent time intervals, a second buffer amplifier coupled between the input and the second ADC bank. The first ADC bank has associated therewith a first dummy sampler, wherein the ADC circuit is configured to activate the first dummy sampler before the start of the first time interval. The second ADC bank has associated therewith a second dummy sampler, wherein the ADC circuit is configured to activate the second dummy sampler before the start of the second time interval.

    Digital-to-analog converter, transmitter, base station and mobile device
    19.
    发明授权
    Digital-to-analog converter, transmitter, base station and mobile device 有权

    公开(公告)号：US10938404B1

    公开(公告)日：2021-03-02

    申请号：US16728163

    申请日：2019-12-27

    Applicant: Intel Corporation

    Inventor： Ramon Sanchez ,  Kameran Azadet ,  Martin Clara ,  Daniel Gruber

    IPC: H03M1/66 ,  H03K3/84 ,  G06F7/58 ,  H04B1/40 ,  H04W88/08

    Abstract: A digital-to-analog converter is provided. The digital-to-analog converter comprises an input configured to receiving a first digital control code for controlling a plurality of digital-to-analog converter cells. Further, the digital-to-analog converter comprises a code converter circuit configured to converter the first digital control code to a second digital control code. Further, the digital-to-analog converter comprises a shift code generation circuit configured to generate a shift code based on a code difference between the first digital control code and a third digital control code. The digital-to-analog converter additionally comprises a bit-shifter circuit configured to bit-shift the second digital control code based on the shift code in order to obtain a modified second digital control code. The digital-to-analog converter comprises a cell activation circuit configured to selectively activate one or more of the plurality of digital-to-analog converter cells based on the modified second digital control code. Each activated digital-to-analog converter cell is configured to output a respective cell output signal. Further, the digital-to-analog converter comprises an output configured to output an analog output signal based on the cell output signals.

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