公开(公告)号：US20180219797A1

公开(公告)日：2018-08-02

申请号：US15620376

申请日：2017-06-12

Applicant: Intel Corporation

Inventor： Sujoy Sen ,  Mohan J. Kumar ,  Donald L. Faw ,  Susanne M. Balle ,  Narayan Ranganathan

IPC: H04L12/927 ,  H04L29/08 ,  H04L12/865

CPC classification number: H04L47/803 ,  H04L47/6275 ,  H04L49/109 ,  H04L67/1097 ,  H04L67/34

Abstract: Technologies for pooling accelerators over fabric are disclosed. In the illustrative embodiment, an application may access an accelerator device over an application programming interface (API) and the API can access an accelerator device that is either local or a remote accelerator device that is located on a remote accelerator sled over a network fabric. The API may employ a send queue and a receive queue to send and receive command capsules to and from the accelerator sled.

公开(公告)号：US12045640B2

公开(公告)日：2024-07-23

申请号：US16909084

申请日：2020-06-23

Applicant: Intel Corporation

Inventor： Sanjay K. Kumar ,  Philip Lantz ,  Rajesh Sankaran ,  Narayan Ranganathan ,  Saurabh Gayen ,  David A. Koufaty ,  Utkarsh Y. Kakaiya

IPC: G06F9/455 ,  G06F9/34 ,  G06F9/48 ,  G06F12/10 ,  G06F12/109 ,  G06F12/14

CPC classification number: G06F9/45558 ,  G06F9/342 ,  G06F9/4875 ,  G06F12/10 ,  G06F12/109 ,  G06F12/1441 ,  G06F2009/45579 ,  G06F2009/45583 ,  G06F12/145 ,  G06F12/1475 ,  G06F12/1483 ,  G06F2212/1016 ,  G06F2212/152 ,  G06F2212/656 ,  G06F2212/657

Abstract: In one embodiment, a data mover accelerator is to receive, from a first agent having a first address space and a first process address space identifier (PASID) to identify the first address space, a first job descriptor comprising a second PASID selector to specify a second PASID to identify a second address space. In response to the first job descriptor, the data mover accelerator is to securely access the first address space and the second address space. Other embodiments are described and claimed.

公开(公告)号：US20230032586A1

公开(公告)日：2023-02-02

申请号：US17711928

申请日：2022-04-01

Applicant: Intel Corporation

Inventor： Narayan Ranganathan ,  Philip R. Lantz ,  Rajesh M. Sankaran ,  Sanjay Kumar ,  Saurabh Gayen ,  Nikhil Rao ,  Utkarsh Y. Kakaiya ,  Dhananjay A. Joshi ,  David Jiang ,  Ashok Raj

IPC: G06F3/06 ,  G06F9/455

Abstract: Methods and apparatus relating to scalable access control checking for cross-address-space data movement are described. In an embodiment, a memory stores an InterDomain Permissions Table (IDPT) having a plurality of entries. At least one entry of the IDPT provides a relationship between a target address space identifier and a plurality of requester address space identifiers. A hardware accelerator device allows access to a target address space, corresponding to the target address space identifier, by one or more of requesters, corresponding to the plurality of requester address space identifiers, respectively, based at least in part on the relationship provided by the at least one entry of the IDPT. Other embodiments are also disclosed and claimed.

公开(公告)号：US11301407B2

公开(公告)日：2022-04-12

申请号：US16242928

申请日：2019-01-08

Applicant: Intel Corporation

Inventor： Sujoy Sen ,  Narayan Ranganathan

IPC: G06F11/20 ,  G06F13/40 ,  G06F3/06 ,  G06F15/173 ,  G06F9/455 ,  H04L69/16 ,  H04L67/141

Abstract: Technologies for accessing pooled accelerator resources over a network fabric are disclosed. In disclosed embodiments, an application hosted by a computing platform accesses remote accelerator resources over a network fabric using protocol multipathing mechanisms. A communication session is established with the remote accelerator resources. The communication session comprises at least two connections. The at least two connections at least include a first connection having or utilizing a first transport layer and a second connection having or utilizing a second transport layer that is different than the first transport layer. Other embodiments may be disclosed and/or claimed.

公开(公告)号：US11178063B2

公开(公告)日：2021-11-16

申请号：US15639641

申请日：2017-06-30

Applicant: INTEL CORPORATION

Inventor： Francesc Guim Bernat ,  Kshitij A. Doshi ,  Mark A. Schmisseur ,  Narayan Ranganathan ,  John Chun Kwok Leung

IPC: H04L12/911 ,  G06F13/40 ,  H04L12/40 ,  G06F9/455 ,  H04L29/08 ,  H04L12/413 ,  H04L12/927

Abstract: A host fabric interface (HFI) apparatus, including: an HFI to communicatively couple to a fabric; and a remote hardware acceleration (RHA) engine to: query an orchestrator via the fabric to identify a remote resource having an accelerator; and send a remote accelerator request to the remote resource via the fabric.

公开(公告)号：US20200341904A1

公开(公告)日：2020-10-29

申请号：US16395891

申请日：2019-04-26

Applicant: Intel Corporation

Inventor： Anjaneya Reddy Chagam Reddy ,  Scott D. Peterson ,  Narayan Ranganathan

IPC: G06F12/10

Abstract: Technologies for accelerated memory lookups include a computing device having a processor and a hardware accelerator. The processor programs the accelerator with a search value, a start pointer, one or more predetermined offsets, and a record length. Each offset may be associated with a pointer type or a value type. The accelerator initializes a memory location at the start pointer and increments the memory location by the offset. The accelerator may read a pointer value from an offset, set the memory location to the pointer value, and repeat for additional offsets. The accelerator may read a value from the offset and compare the value to the search value. If the values match, the accelerator returns the address of the matching value to the processor. If the values do not match, the accelerator searches a next record based on the record length. Other embodiments are described and claimed.

公开(公告)号：US20200341824A1

公开(公告)日：2020-10-29

申请号：US16395793

申请日：2019-04-26

Applicant: Intel Corporation

Inventor： Susanne M. Balle ,  Evan Custodio ,  Narayan Ranganathan ,  Paul H. Dormitzer

IPC: G06F9/54 ,  G06F9/38 ,  G06F15/173

Abstract: Technologies for providing inter-kernel communication abstraction to support scale-up and scale-out include an accelerator device. The accelerator device includes circuitry to receive, from a kernel of the present accelerator device, a request through an application programming interface exposed to a high level software language in which the kernel of the present accelerator device is implemented, to establish a logical communication path between the kernel of the present accelerator device and a target accelerator device kernel, based on one or more physical communication paths. Additionally, the circuitry is to establish, in response to the request, the logical communication path between the kernel of the present accelerator device and the other accelerator device kernel and communicate data between the kernel of the present accelerator device and the other accelerator device kernel with a unified communication protocol that manages differences between the physical communication paths.

公开(公告)号：US10509738B2

公开(公告)日：2019-12-17

申请号：US15201373

申请日：2016-07-01

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Thomas Willhalm ,  Narayan Ranganathan ,  Pete D. Vogt

IPC: G06F13/16 ,  G06F13/40 ,  G06F13/42 ,  H04L12/803 ,  H04L29/08 ,  G06F15/173 ,  H04L12/933

Abstract: An extension of node architecture and proxy requests enables a node to expose memory computation capability to remote nodes. A remote node can request execution of an operation by a remote memory computation resource, and the remote memory computation resource can execute the request locally and return the results of the computation. The node includes processing resources, a fabric interface, and a memory subsystem including a memory computation resource. The local execution of the request by the memory computation resource can reduce latency and bandwidth concerns typical with remote requests.

公开(公告)号：US09389942B2

公开(公告)日：2016-07-12

申请号：US14057485

申请日：2013-10-18

Applicant: Intel Corporation

Inventor： Ashok Raj ,  Narayan Ranganathan

IPC: G06F11/00 ,  G06F11/07

CPC classification number: G06F11/079 ,  G06F11/0706 ,  G06F11/0751 ,  G06F11/0787 ,  G06F11/1417 ,  G06F2201/805

Abstract: A computing system can include a machine check counter (MCC) including a current value. The current value indicates a system reboot resetting hardware of the computing system. The machine check counter includes a model specific register including a counter indicating the current value, the current value to be incremented upon the system reboot.

Abstract translation: 计算系统可以包括包括当前值的机器检查计数器（MCC）。 当前值表示计算系统的系统重新启动重置硬件。 机器检查计数器包括一个特定于型号的寄存器，包括一个指示当前值的计数器，当系统重启时增加的当前值。

公开(公告)号：US20160087847A1

公开(公告)日：2016-03-24

申请号：US14494892

申请日：2014-09-24

Applicant: INTEL CORPORATION

Inventor： Ramamurthy Krithivas ,  Narayan Ranganathan ,  Mohan J. Kumar ,  John C. Leung

IPC: H04L12/24 ,  H04L12/855 ,  H04L29/12

CPC classification number: H04L41/12 ,  H04L41/044 ,  H04L47/2466 ,  H04L61/2015 ,  H04L61/2507

Abstract: Mechanisms to enable management controllers to learn the control plane hierarchy in data center environments. The data center is configured in a physical hierarchy including multiple pods, racks, trays, and sleds and associated switches. Management controllers at various levels in a control plane hierarchy and associated with switches in the physical hierarchy are configured to add their IP addresses to DHCP (Dynamic Host Control Protocol) responses that are generated by a DCHP server in response to DCHP requests for IP address requests initiated by DHCP clients including manageability controllers, compute nodes and storage nodes in the data center. As the DCHP response traverses each of multiple switches along a forwarding path from the DCHP server to the DHCP client, an IP address of the manageability controller associated with the switch is inserted. Upon receipt at the DHCP client, the inserted IP addresses are extracted and used to automate learning of the control plane hierarchy.

Abstract translation: 允许管理控制器在数据中心环境中学习控制平面层次的机制。 数据中心配置在物理层次结构中，包括多个pod，rack，tray以及sleds和关联的switch。 配置在控制平面层级中并与物理层次结构中的交换机相关联的管理控制器被配置为将其IP地址添加到由DCHP服务器响应于对于IP地址请求的DCHP请求而产生的DHCP（动态主机控制协议）响应 由DHCP客户端启动，包括数据中心中的可管理性控制器，计算节点和存储节点。 随着DCHP响应遍历从DCHP服务器到DHCP客户端的转发路径的多个交换机中的每一个，插入与交换机相关联的可管理性控制器的IP地址。 在DHCP客户端收到后，插入的IP地址被提取并用于自动化控制平面层次结构的学习。