公开(公告)号：US11620358B2

公开(公告)日：2023-04-04

申请号：US16411730

申请日：2019-05-14

Applicant: Intel Corporation

Inventor： Chetan Chauhan ,  Rajesh Sundaram ,  Richard Coulson ,  Bruce Querbach ,  Jawad B. Khan ,  Shigeki Tomishima ,  Srikanth Srinivasan

IPC: G06F17/16 ,  G06F9/30

Abstract: Technologies for performing in-memory macro operations include a memory having a media access circuitry connected to a memory media. The media access circuitry is to receive a request to perform an in-memory macro operation indicative of a set of multiple in-memory operations. The media access circuitry is also to perform, in response to the request, the in-memory macro operation on data present in the memory media.

公开(公告)号：US11604834B2

公开(公告)日：2023-03-14

申请号：US16870003

申请日：2020-05-08

Applicant: Intel Corporation

Inventor： Mariano Tepper ,  Dipanjan Sengupta ,  Sourabh Dongaonkar ,  Chetan Chauhan ,  Jawad Khan ,  Theodore Willke ,  Richard Coulson ,  Rajesh Sundaram

IPC: G06F16/903 ,  G06F17/16 ,  G06K9/62

Abstract: Technologies for performing stochastic similarity searches in an online clustering space include a device having a column addressable memory and circuitry. The circuitry is configured to determine a Hamming distance from a binary dimensionally expanded vector to each cluster of a set of clusters of binary dimensionally expanded vectors in the memory, identify the cluster having the smallest Hamming distance from the binary dimensionally expanded vector, determine whether the identified cluster satisfies a target size, and add or delete, in response to a determination that the identified cluster does not satisfy the target size, the binary dimensionally expanded vector to or from the identified cluster.

公开(公告)号：US11526279B2

公开(公告)日：2022-12-13

申请号：US15930035

申请日：2020-05-12

Applicant: Intel Corporation

Inventor： Zion Kwok ,  Jawad Khan ,  Richard Coulson

IPC: G06F3/06 ,  G06F7/72

Abstract: Technologies for scrambling functions in a column-addressable memory architecture includes a device having a memory and a circuitry. The memory includes a matrix storing individually addressable bit data, and the matrix is formed by rows and columns. The circuitry is to receive a request to perform a write operation of one or more bit values to one of the columns. The circuitry is further to determine a scrambler state at each location of the column, the location corresponding to a respective row and column index. The scrambler state is indicative of a function used to determine a value at the respective column location. Each of the bit values is scrambled as a function of the scrambler state for the respective column location and written thereto.

公开(公告)号：US11074008B2

公开(公告)日：2021-07-27

申请号：US16369996

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Jawad B. Khan ,  Richard Coulson

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/02 ,  G06F9/30 ,  G06F11/10

Abstract: Technologies for performing a hyper-dimensional operation in a memory of the compute device include a memory and a memory controller. The memory controller is configured to receive a query from a requestor and determine, in response to a receipt of the query, a key hyper-dimensional vector associated with the query, perform a hyper-dimensional operation to determine a reference hyper-dimensional vector associated with a value to the key. The memory controller is further configured to perform a nearest neighbor search by searching columns of a stochastic associative array of a hyper-dimensional vector table in the memory, identify a closest matching row in the stochastic associative array relative to the reference hyper-dimensional vector, wherein the closest matching row indicates a closest matching value hyper-dimensional vector, and output a value associated with the closest matching value hyper-dimensional vector.

公开(公告)号：US20200265045A1

公开(公告)日：2020-08-20

申请号：US16868069

申请日：2020-05-06

Applicant: Intel Corporation

Inventor： Mariano Tepper ,  Dipanjan Sengupta ,  Jawad Khan ,  Sourabh Dongaonkar ,  Chetan Chauhan ,  Richard Coulson ,  Theodore Willke

IPC: G06F16/2458 ,  G06F16/248 ,  G06N20/00 ,  G06N7/00

Abstract: Technologies for refining stochastic similarity search candidates include a device having a memory that is column addressable and circuitry connected to the memory. The circuitry is configured to add a set of input data vectors to the memory as a set of binary dimensionally expanded vectors, including multiplying each input data vector with a projection matrix. The circuitry is also configured to produce a search hash code from a search data vector, including multiplying the search data vector with the projection matrix. Additionally, the circuitry is configured to identify a result set of the binary dimensionally expanded vectors as a function of a Hamming distance of each binary dimensionally expanded vector from the search hash code and determine, from the result set, a refined result set as a function of a similarity measure in an original input space of the input data vectors.

公开(公告)号：US20200264874A1

公开(公告)日：2020-08-20

申请号：US16867948

申请日：2020-05-06

Applicant: Intel Corporation

Inventor： Mariano Tepper ,  Dipanjan Sengupta ,  Sourabh Dongaonkar ,  Chetan Chauhan ,  Jawad Khan ,  Theodore Willke ,  Richard Coulson

IPC: G06F9/30 ,  G06F7/58 ,  G06F16/13 ,  H01L27/06

Abstract: Technologies for performing random sparse lifting and Procrustean orthogonal sparse hashing using column read-enabled memory include a device that has a memory that is column addressable and circuitry connected to the memory. The circuitry is configured to add a set of input data vectors to the memory as a set of binary dimensionally expanded vectors, including multiplying each input data vector with a projection matrix. The circuitry is also configured to produce a search hash code from a search data vector, including multiplying the search data vector with the projection matrix. Further, the circuitry is configured to determine a Hamming distance between the search hash code and each of the binary dimensionally expanded vectors.

公开(公告)号：US20190227808A1

公开(公告)日：2019-07-25

申请号：US16370013

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Jawad B. Khan ,  Richard Coulson

IPC: G06F9/38 ,  G06F9/30 ,  G06F15/80

Abstract: Technologies for performing hyper-dimensional operations in memory includes a device with a memory media and a memory controller. The memory controller is configured to receive a query from a requestor and determine, in response to receiving the query, a reference hyper-dimensional vector associated with the query. The memory controller is further configured to perform a nearest neighbor search by searching columns of a stochastic associative array in the memory media to determine a number of matching bit values for each row relative to the reference hyper-dimensional vector, wherein each bit in a column of the stochastic associative array represents a bit value of a corresponding row, identify a closest matching row that has a highest number of matching bit values, and output data of the closest matching row.

公开(公告)号：US11574172B2

公开(公告)日：2023-02-07

申请号：US16361432

申请日：2019-03-22

Applicant: Intel Corporation

Inventor： Dipanjan Sengupta ,  Jawad B. Khan ,  Theodore Willke ,  Richard Coulson

IPC: G06N3/063 ,  G06F3/06 ,  G06N3/04

Abstract: Technologies for efficiently performing memory augmented neural network (MANN) update operations includes a device with circuitry configured to obtain a key usable to search a memory associated with a memory augmented neural network for one or more data sets. The circuitry is also configured to perform a stochastic associative search to identify a group of data sets within the memory that satisfy the key and write to the identified group of data sets concurrently to update the memory augmented neural network.

公开(公告)号：US20220405005A1

公开(公告)日：2022-12-22

申请号：US17349592

申请日：2021-06-16

Applicant: Intel Corporation

Inventor： Scott Weber ,  Jawad Khan ,  Ilya Ganusov ,  Martin Langhammer ,  Matthew Adiletta ,  Terence Magee ,  Albert Fazio ,  Richard Coulson ,  Ravi Gutala ,  Aravind Dasu ,  Mahesh Iyer

IPC: G06F3/06

Abstract: A three dimensional circuit system includes a first integrated circuit die having a core logic region that has first memory circuits and logic circuits. The three dimensional circuit system includes a second integrated circuit die that has second memory circuits. The first and second integrated circuit dies are coupled together in a vertically stacked configuration. The three dimensional circuit system includes third memory circuits coupled to the first integrated circuit die. The third memory circuits reside in a plane of the first integrated circuit die. The logic circuits are coupled to access the first, second, and third memory circuits and data can move between the first, second, and third memories. The third memory circuits have a larger memory capacity and a smaller memory access bandwidth than the second memory circuits. The second memory circuits have a larger memory capacity and a smaller memory access bandwidth than the first memory circuits.

公开(公告)号：US11416170B2

公开(公告)日：2022-08-16

申请号：US16249964

申请日：2019-01-17

Applicant: Intel Corporation

Inventor： Jawad B. Khan ,  Richard Coulson

IPC: G06F3/06 ,  G06F12/06 ,  G06F12/02

Abstract: Technologies for efficiently accessing data columns and rows in a memory include a device with circuitry configured to receive a request to access memory in which each bit of a logical column of bits is located in a different physical row and a different physical column than any other bit in the logical column. The circuitry is additionally configured to access, in response to the request, the memory. In accessing the memory, the circuitry rotates one or more bit positions in a data set read from or written to the memory.