公开(公告)号：US12034085B2

公开(公告)日：2024-07-09

申请号：US17848275

申请日：2022-06-23

Applicant: Intel Corporation

Inventor： Harald Gossner ,  Peter Baumgartner ,  Uwe Hodel ,  Domagoj Siprak ,  Stephan Leuschner ,  Richard Geiger ,  Han Wui Then ,  Marko Radosavljevic ,  Sansaptak Dasgupta

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/20 ,  H01L29/778 ,  H01L29/93

CPC classification number: H01L29/93 ,  H01L29/0649 ,  H01L29/2003 ,  H01L29/778

Abstract: A variable capacitance III-N device having multiple two-dimensional electron gas (2DEG) layers are described. In some embodiments, the device comprises a first source and a first drain; a first polarization layer adjacent to the first source and the first drain; a first channel layer coupled to the first source and the first drain and adjacent to the first polarization layer, the first channel layer comprising a first 2DEG region; a second source and a second drain; a second polarization layer adjacent to the second source and the second drain; and a second channel layer coupled to the second source and the second drain and adjacent to the second polarization layer, the second channel layer comprising a second 2DEG region, wherein the second channel layer is over the first polarization layer.

公开(公告)号：US20230197598A1

公开(公告)日：2023-06-22

申请号：US17554004

申请日：2021-12-17

Applicant: Intel Corporation

Inventor： Georgios Panagopoulos ,  Richard Geiger ,  Peter Baumgartner ,  Harald Gossner ,  Uwe Hodel ,  Michael Langenbuch ,  Johannes Xaver Rauh ,  Alexander Bechtold ,  Richard Hudeczek ,  Carla Moran Guizan

IPC: H01L23/522 ,  H01L21/8238 ,  H01L23/528 ,  H01L23/535 ,  H01L27/092

CPC classification number: H01L23/5226 ,  H01L21/823821 ,  H01L21/823871 ,  H01L23/5286 ,  H01L23/535 ,  H01L27/0924

Abstract: IC devices including inductors or transformers formed based on BPRs are disclosed. An example IC device includes semiconductor structures of one or more transistors, an electrically conductive layer, a support structure comprising a semiconductor material, and an inductor. The inductor includes an electrical conductor constituted by a power rail buried in the support structure. The inductor also includes a magnetic core coupled to the electrical conductor. The magnetic core includes magnetic rails buried in the support structure, magnetic TSVs buried in the support structure, and a magnetic plate at the backside of the support structure. The magnetic core includes a magnetic material, such as Fe, NiFe, CoZrTa, etc. In some embodiments, the IC device includes another power rail that is buried in the support structure and constitutes another electrical conductor coupled to the magnetic core. The two power rails and magnetic core can constitute a transformer.

公开(公告)号：US11380806B2

公开(公告)日：2022-07-05

申请号：US16641222

申请日：2017-09-28

Applicant: INTEL CORPORATION

Inventor： Harald Gossner ,  Peter Baumgartner ,  Uwe Hodel ,  Domagoj Siprak ,  Stephan Leuschner ,  Richard Geiger ,  Han Wui Then ,  Marko Radosavljevic ,  Sansaptak Dasgupta

IPC: H01L29/93 ,  H01L29/06 ,  H01L29/20 ,  H01L29/778

Abstract: A variable capacitance III-N device having multiple two-dimensional electron gas (2DEG) layers are described. In some embodiments, the device comprises a first source and a first drain; a first polarization layer adjacent to the first source and the first drain; a first channel layer coupled to the first source and the first drain and adjacent to the first polarization layer, the first channel layer comprising a first 2DEG region; a second source and a second drain; a second polarization layer adjacent to the second source and the second drain; and a second channel layer coupled to the second source and the second drain and adjacent to the second polarization layer, the second channel layer comprising a second 2DEG region, wherein the second channel layer is over the first polarization layer.

公开(公告)号：US20200220030A1

公开(公告)日：2020-07-09

申请号：US16641222

申请日：2017-09-28

Applicant: INTEL CORPORATION

Inventor： Harald Gossner ,  Peter Baumgartner ,  Uwe Hodel ,  Domagoj Siprak ,  Stephan Leuschner ,  Richard Geiger ,  Han Wui Then ,  Marko Radosavljevic ,  Sansaptak Dasgupta

IPC: H01L29/93 ,  H01L29/20 ,  H01L29/06 ,  H01L29/778

Abstract: A variable capacitance III-N device having multiple two-dimensional electron gas (2DEG) layers are described. In some embodiments, the device comprises a first source and a first drain; a first polarization layer adjacent to the first source and the first drain; a first channel layer coupled to the first source and the first drain and adjacent to the first polarization layer, the first channel layer comprising a first 2DEG region; a second source and a second drain; a second polarization layer adjacent to the second source and the second drain; and a second channel layer coupled to the second source and the second drain and adjacent to the second polarization layer, the second channel layer comprising a second 2DEG region, wherein the second channel layer is over the first polarization layer.

公开(公告)号：US20240322775A1

公开(公告)日：2024-09-26

申请号：US18187001

申请日：2023-03-21

Applicant: Intel Corporation

Inventor： Telesphor Kamgaing ,  Peter Baumgartner ,  Steven Callender ,  Richard Geiger ,  Harald Gossner ,  Jonathan Jensen

IPC: H03F3/60 ,  H01L23/66 ,  H03F3/195 ,  H03F3/24

CPC classification number: H03F3/602 ,  H01L23/66 ,  H03F3/195 ,  H03F3/245 ,  H01L2223/6677 ,  H03F2200/294 ,  H03F2200/451

Abstract: Disclosed herein are electronic assemblies, integrated circuit (IC) packages, and communication devices implementing three-dimensional power combiners. An electronic assembly may include a first die, comprising a first transmission line, and a second die, comprising a second transmission line. Each die includes a first face and an opposing second face, and the second die is stacked above the first die so that the first face of the second die is coupled to the second face of the first die. The electronic assembly further includes a first conductive pathway between one end of the first transmission line and a first connection point at the first face of the first die, a second conductive pathway between one end of the second transmission line and a second connection point at the first face of the first die, and a third conductive pathway between the other ends of the first and second transmission lines.

公开(公告)号：US20230207464A1

公开(公告)日：2023-06-29

申请号：US17552683

申请日：2021-12-16

Applicant: Intel Corporation

Inventor： Richard Geiger ,  Georgios Panagopoulos ,  Johannes Xaver Rauh ,  Harald Gossner

IPC: H01L23/528

CPC classification number: H01L23/5286

Abstract: IC devices including IC devices including BPRs that form metal-semiconductor junctions with semiconductor sections where the BPRs are partially buried are disclosed. An example IC device includes a first layer comprising semiconductor structures, such as fins, nanowires, or nanoribbons. The IC device also includes a layer comprising an electrically conductive material and coupled to the semiconductor structures. The IC device further includes a support structure comprising a BPR and a semiconductor section. The BPR contacts with the semiconductor section and forms a metal-semiconductor junction. The metal-semiconductor junction constitutes a Schottky barrier for electrons. The IC device may include a SCR including a sequence of p-well, n-well, p-well, and n-well with Schottky barriers in the first p-well and the second n-well. The Schottky barrier may also be used as a guard ring to extract injected charge carriers.

公开(公告)号：US20230197527A1

公开(公告)日：2023-06-22

申请号：US17554061

申请日：2021-12-17

Applicant: Intel Corporation

Inventor： Richard Geiger ,  Peter Baumgartner ,  Alexander Bechtold ,  Uwe Hodel ,  Richard Hudeczek ,  Walther Lutz ,  Carla Moran Guizan ,  Georgios Panagopoulos ,  Johannes Xaver Rauh ,  Roshini Sachithanandan

IPC: H01L21/8238 ,  H01L23/528 ,  H01L23/535 ,  H01L23/522 ,  H01L27/092

CPC classification number: H01L21/823871 ,  H01L21/823821 ,  H01L23/5286 ,  H01L23/535 ,  H01L23/5226 ,  H01L27/0924

Abstract: IC devices including semiconductor devices isolated by BSRs are disclosed. An example IC device includes a first and a second semiconductor devices, a support structure, and a BSR. The BSR defines boundaries of a first and second section in the support structure. At least a portion of the first semiconductor device is in the first section, and at least a portion of the second semiconductor device is in the second section. The first semiconductor device is isolated from the second semiconductor device by the BSR. Signals from the first semiconductor device would not be transmitted to the second semiconductor device through the support structure. The BSR may be connected to a TSV or be biased. The IC device may include additional BSRs to isolate the first and second semiconductor devices. An BSR may be a power rail used for delivering power.

公开(公告)号：US20230163120A1

公开(公告)日：2023-05-25

申请号：US17530618

申请日：2021-11-19

Applicant: Intel Corporation

Inventor： Richard Geiger ,  Georgios Panagopoulos ,  Johannes Xaver Rauh ,  Harald Gossner

IPC: H01L27/02 ,  H01L29/868 ,  H01L29/872 ,  H01L29/66

CPC classification number: H01L27/0296 ,  H01L27/0255 ,  H01L29/868 ,  H01L29/872 ,  H01L29/66143 ,  H01L29/66136

Abstract: Disclosed herein are IC devices, packages, and device assemblies that include diodes arranged so that their first and second terminals may be contacted from the opposite faces of a support structure. Such diodes are referred to herein as “vertical diodes” to reflect the fact that the diode extends, in a vertical direction (i.e., in a direction perpendicular to the support structure), between the bottom and the top of support structures. Vertical diodes as described herein may introduce additional degrees of freedom in diode choices in terms of, e.g., high-voltage handling, capacitance modulation, and speed.

公开(公告)号：US11424354B2

公开(公告)日：2022-08-23

申请号：US16642867

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Harald Gossner ,  Peter Baumgartner ,  Uwe Hodel ,  Domagoj Siprak ,  Stephan Leuschner ,  Richard Geiger

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/20

Abstract: A Group III-Nitride (III-N) device structure is provided comprising: a heterostructure having three or more layers comprising III-N material, an anode n+ region and a cathode comprising donor dopants, wherein the anode n+ region and the cathode are on the first layer of the heterostructure and wherein the anode n+ region and the cathode extend beyond the heterostructure, and an anode metal region within a recess that extends through two or more of the layers, wherein the anode metal region is in electrical contact with the first layer, wherein the anode metal region comprises a first width within the recess and a second width beyond the recess, and wherein the anode metal region is coupled with the anode n+ region. Other embodiments are also disclosed and claimed.