-
公开(公告)号:US11545586B2
公开(公告)日:2023-01-03
申请号:US16643929
申请日:2017-09-29
Applicant: INTEL CORPORATION
Inventor: Harald Gossner , Peter Baumgartner , Uwe Hodel , Domagoj Siprak , Stephan Leuschner , Richard Geiger , Han Wui Then , Marko Radosavljevic , Sansaptak Dasgupta
IPC: H01L29/872 , H01L29/20 , H01L29/66 , H01L29/205
Abstract: A Group III-Nitride (III-N) device structure is provided which comprises: a heterostructure having three or more layers comprising III-N material, an anode within a recess that extends through two or more of the layers, wherein the anode is in electrical contact with the first layer, a cathode comprising donor dopants, wherein the cathode is on the first layer of the heterostructure; and a conducting region in the first layer in direct contact to the cathode and conductively connected to the anode. Other embodiments are also disclosed and claimed.
-
公开(公告)号:US11373995B2
公开(公告)日:2022-06-28
申请号:US16643928
申请日:2017-09-29
Applicant: INTEL CORPORATION
Inventor: Harald Gossner , Peter Baumgartner , Uwe Hodel , Domagoj Siprak , Stephan Leuschner , Richard Geiger , Han Wui Then , Marko Radosavljevic , Sansaptak Dasgupta
IPC: H01L29/778 , H01L27/02 , H01L21/8252 , H01L27/06 , H01L29/20 , H01L29/205 , H01L29/47 , H01L29/66 , H01L29/872 , H01L27/07
Abstract: A Group III-Nitride (III-N) device structure is presented comprising: a heterostructure having three or more layers comprising III-N material, a cathode comprising donor dopants, wherein the cathode is on a first layer of the heterostructure,
an anode within a recess that extends through two or more of the layers of the heterostructure, wherein the anode comprises a first region wherein the anode is separated from the heterostructure by a high k dielectric material, and a second region wherein the anode is in direct contact with the heterostructure, and a conducting region in the first layer in direct contact to the cathode and conductively connected to the anode. Other embodiments are also disclosed and claimed.-
公开(公告)号:US12034085B2
公开(公告)日:2024-07-09
申请号:US17848275
申请日:2022-06-23
Applicant: Intel Corporation
Inventor: Harald Gossner , Peter Baumgartner , Uwe Hodel , Domagoj Siprak , Stephan Leuschner , Richard Geiger , Han Wui Then , Marko Radosavljevic , Sansaptak Dasgupta
IPC: H01L29/66 , H01L29/06 , H01L29/20 , H01L29/778 , H01L29/93
CPC classification number: H01L29/93 , H01L29/0649 , H01L29/2003 , H01L29/778
Abstract: A variable capacitance III-N device having multiple two-dimensional electron gas (2DEG) layers are described. In some embodiments, the device comprises a first source and a first drain; a first polarization layer adjacent to the first source and the first drain; a first channel layer coupled to the first source and the first drain and adjacent to the first polarization layer, the first channel layer comprising a first 2DEG region; a second source and a second drain; a second polarization layer adjacent to the second source and the second drain; and a second channel layer coupled to the second source and the second drain and adjacent to the second polarization layer, the second channel layer comprising a second 2DEG region, wherein the second channel layer is over the first polarization layer.
-
公开(公告)号:US11380806B2
公开(公告)日:2022-07-05
申请号:US16641222
申请日:2017-09-28
Applicant: INTEL CORPORATION
Inventor: Harald Gossner , Peter Baumgartner , Uwe Hodel , Domagoj Siprak , Stephan Leuschner , Richard Geiger , Han Wui Then , Marko Radosavljevic , Sansaptak Dasgupta
IPC: H01L29/93 , H01L29/06 , H01L29/20 , H01L29/778
Abstract: A variable capacitance III-N device having multiple two-dimensional electron gas (2DEG) layers are described. In some embodiments, the device comprises a first source and a first drain; a first polarization layer adjacent to the first source and the first drain; a first channel layer coupled to the first source and the first drain and adjacent to the first polarization layer, the first channel layer comprising a first 2DEG region; a second source and a second drain; a second polarization layer adjacent to the second source and the second drain; and a second channel layer coupled to the second source and the second drain and adjacent to the second polarization layer, the second channel layer comprising a second 2DEG region, wherein the second channel layer is over the first polarization layer.
-
公开(公告)号:US20220166430A1
公开(公告)日:2022-05-26
申请号:US17669762
申请日:2022-02-11
Applicant: Intel Corporation
Inventor: Chuanzhao Yu , Stephan Leuschner , David Newman
IPC: H03K17/693 , H03H7/42 , H03K17/06 , H03K17/16
Abstract: Techniques are provided for fanning out a signal from a balun. In various aspects, the system can include a balun configured to receive a signal for transmission at an input and to provide a representation of the signal at an output, a plurality of pass gate circuits, each pass gate circuit configured to receive the representation of the signal at a first node, to receive a control signal at a second node to pass the representation of the signal to a third node when the control signal is in a first state, and to isolate the representation of the signal from the third node when the control signal is in a second state. The first state of the control signal can include a non-zero voltage, and the second state of the control signal can include the non-zero voltage with a polarity opposite the non-zero voltage of the first state.
-
公开(公告)号:US20200220030A1
公开(公告)日:2020-07-09
申请号:US16641222
申请日:2017-09-28
Applicant: INTEL CORPORATION
Inventor: Harald Gossner , Peter Baumgartner , Uwe Hodel , Domagoj Siprak , Stephan Leuschner , Richard Geiger , Han Wui Then , Marko Radosavljevic , Sansaptak Dasgupta
IPC: H01L29/93 , H01L29/20 , H01L29/06 , H01L29/778
Abstract: A variable capacitance III-N device having multiple two-dimensional electron gas (2DEG) layers are described. In some embodiments, the device comprises a first source and a first drain; a first polarization layer adjacent to the first source and the first drain; a first channel layer coupled to the first source and the first drain and adjacent to the first polarization layer, the first channel layer comprising a first 2DEG region; a second source and a second drain; a second polarization layer adjacent to the second source and the second drain; and a second channel layer coupled to the second source and the second drain and adjacent to the second polarization layer, the second channel layer comprising a second 2DEG region, wherein the second channel layer is over the first polarization layer.
-
公开(公告)号:US11424354B2
公开(公告)日:2022-08-23
申请号:US16642867
申请日:2017-09-29
Applicant: Intel Corporation
Inventor: Harald Gossner , Peter Baumgartner , Uwe Hodel , Domagoj Siprak , Stephan Leuschner , Richard Geiger
IPC: H01L29/778 , H01L29/66 , H01L29/20
Abstract: A Group III-Nitride (III-N) device structure is provided comprising: a heterostructure having three or more layers comprising III-N material, an anode n+ region and a cathode comprising donor dopants, wherein the anode n+ region and the cathode are on the first layer of the heterostructure and wherein the anode n+ region and the cathode extend beyond the heterostructure, and an anode metal region within a recess that extends through two or more of the layers, wherein the anode metal region is in electrical contact with the first layer, wherein the anode metal region comprises a first width within the recess and a second width beyond the recess, and wherein the anode metal region is coupled with the anode n+ region. Other embodiments are also disclosed and claimed.
-
公开(公告)号:US11632108B2
公开(公告)日:2023-04-18
申请号:US17669762
申请日:2022-02-11
Applicant: Intel Corporation
Inventor: Chuanzhao Yu , Stephan Leuschner , David Newman
IPC: H03K17/693 , H03H7/42 , H03K17/06 , H03K17/16
Abstract: Techniques are provided for fanning out a signal from a balun. In various aspects, the system can include a balun configured to receive a signal for transmission at an input and to provide a representation of the signal at an output, a plurality of pass gate circuits, each pass gate circuit configured to receive the representation of the signal at a first node, to receive a control signal at a second node to pass the representation of the signal to a third node when the control signal is in a first state, and to isolate the representation of the signal from the third node when the control signal is in a second state. The first state of the control signal can include a non-zero voltage, and the second state of the control signal can include the non-zero voltage with a polarity opposite the non-zero voltage of the first state.
-
公开(公告)号:US11283444B2
公开(公告)日:2022-03-22
申请号:US16766843
申请日:2018-03-28
Applicant: Intel Corporation
Inventor: Chuanzhao Yu , Stephan Leuschner , David Newman
IPC: H03K17/693 , H03H7/42 , H03K17/06 , H03K17/16
Abstract: Techniques are provided for fanning out a signal from a balun. In various aspects, the system can include a balun configured to receive a signal for transmission at an input and to provide a representation of the signal at an output, a plurality of pass gate circuits, each pass gate circuit configured to receive the representation of the signal at a first node, to receive a control signal at a second node to pass the representation of the signal to a third node when the control signal is in a first state, and to isolate the representation of the signal from the third node when the control signal is in a second state. The first state of the control signal can include a non-zero voltage, and the second state of the control signal can include the non-zero voltage with a polarity opposite the non-zero voltage of the first state.
-
10.
公开(公告)号:US11575036B2
公开(公告)日:2023-02-07
申请号:US16651327
申请日:2017-09-28
Applicant: Intel Corporation
Inventor: Han Wui Then , Stephan Leuschner , Marko Radosavljevic , Sansaptak Dasgupta
IPC: H01L29/40 , H01L29/778 , H01L21/285 , H01L21/765 , H01L29/20 , H01L29/205 , H01L29/423 , H01L29/66 , H03F3/21 , H03F3/45
Abstract: Gallium nitride (GaN) transistors with source and drain field plates are described. In an example, a transistor includes a gallium nitride (GaN) layer above a substrate, a gate structure over the GaN layer, a source region on a first side of the gate structure, a drain region on a second side of the gate structure, the second side opposite the first side, a source field plate above the source region, and a drain field plate above the drain region.
-
-
-
-
-
-
-
-
-