公开(公告)号：US20240363556A1

公开(公告)日：2024-10-31

申请号：US18139204

申请日：2023-04-25

Applicant: Intel Corporation

Inventor： Harald Gossner ,  Thomas Wagner ,  Bernd Waidhas ,  Georg Seidemann ,  Tae Young Yang ,  Telesphor Kamgaing

IPC: H01L23/60 ,  H01L23/00 ,  H01L23/66 ,  H01Q1/50 ,  H01Q9/04

CPC classification number: H01L23/60 ,  H01L23/66 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01Q1/50 ,  H01Q9/0457 ,  H01L2223/6672 ,  H01L2223/6677 ,  H01L2224/05556 ,  H01L2224/05557 ,  H01L2224/05571 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/08147 ,  H01L2224/08267 ,  H01L2224/16267 ,  H01L2224/2929 ,  H01L2224/29499 ,  H01L2224/32267 ,  H01L2224/32268

Abstract: An antenna device includes an antenna on a substrate, a low-impedance electrostatic discharge (ESD) path for an ESD pulse from the antenna to a ground terminal, and a signal path between the antenna and either a signal terminal or an integrated circuit (IC) die. The ESD and signal paths may each include separate vias through the substrate. A capacitor may couple a signal to or from the antenna and the signal terminal (or IC die) but block low-frequency power (such as an ESD pulse). The ESD path has an electrical length of a quarter of the wavelength and so may present a high impedance to ground for the signal. The antenna device may include or be coupled to an IC die. The IC die may couple to the signal and ground terminals, e.g., opposite the substrate from the antenna.

公开(公告)号：US11545586B2

公开(公告)日：2023-01-03

申请号：US16643929

申请日：2017-09-29

Applicant: INTEL CORPORATION

Inventor： Harald Gossner ,  Peter Baumgartner ,  Uwe Hodel ,  Domagoj Siprak ,  Stephan Leuschner ,  Richard Geiger ,  Han Wui Then ,  Marko Radosavljevic ,  Sansaptak Dasgupta

IPC: H01L29/872 ,  H01L29/20 ,  H01L29/66 ,  H01L29/205

Abstract: A Group III-Nitride (III-N) device structure is provided which comprises: a heterostructure having three or more layers comprising III-N material, an anode within a recess that extends through two or more of the layers, wherein the anode is in electrical contact with the first layer, a cathode comprising donor dopants, wherein the cathode is on the first layer of the heterostructure; and a conducting region in the first layer in direct contact to the cathode and conductively connected to the anode. Other embodiments are also disclosed and claimed.

公开(公告)号：US11373995B2

公开(公告)日：2022-06-28

申请号：US16643928

申请日：2017-09-29

Applicant: INTEL CORPORATION

Inventor： Harald Gossner ,  Peter Baumgartner ,  Uwe Hodel ,  Domagoj Siprak ,  Stephan Leuschner ,  Richard Geiger ,  Han Wui Then ,  Marko Radosavljevic ,  Sansaptak Dasgupta

IPC: H01L29/778 ,  H01L27/02 ,  H01L21/8252 ,  H01L27/06 ,  H01L29/20 ,  H01L29/205 ,  H01L29/47 ,  H01L29/66 ,  H01L29/872 ,  H01L27/07

Abstract: A Group III-Nitride (III-N) device structure is presented comprising: a heterostructure having three or more layers comprising III-N material, a cathode comprising donor dopants, wherein the cathode is on a first layer of the heterostructure,
an anode within a recess that extends through two or more of the layers of the heterostructure, wherein the anode comprises a first region wherein the anode is separated from the heterostructure by a high k dielectric material, and a second region wherein the anode is in direct contact with the heterostructure, and a conducting region in the first layer in direct contact to the cathode and conductively connected to the anode. Other embodiments are also disclosed and claimed.

公开(公告)号：US09515049B2

公开(公告)日：2016-12-06

申请号：US14368434

申请日：2013-12-19

Applicant: Intel Corporation

Inventor： Sven Albers ,  Michael Skinner ,  Hans-Joachim Barth ,  Peter Baumgartner ,  Harald Gossner

IPC: H01L25/065 ,  H01L23/552 ,  H01L23/522 ,  H01L29/06 ,  H01L23/00 ,  H01L27/02

CPC classification number: H01L25/0652 ,  H01L23/367 ,  H01L23/3675 ,  H01L23/5226 ,  H01L23/5227 ,  H01L23/552 ,  H01L23/562 ,  H01L23/564 ,  H01L23/66 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/48 ,  H01L24/49 ,  H01L24/81 ,  H01L24/85 ,  H01L25/065 ,  H01L25/0657 ,  H01L27/0207 ,  H01L29/0657 ,  H01L2223/6677 ,  H01L2224/131 ,  H01L2224/1319 ,  H01L2224/16105 ,  H01L2224/16113 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/48091 ,  H01L2224/481 ,  H01L2224/48106 ,  H01L2224/4813 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/48482 ,  H01L2224/49 ,  H01L2224/73257 ,  H01L2224/81001 ,  H01L2224/81007 ,  H01L2224/8114 ,  H01L2224/81801 ,  H01L2224/8185 ,  H01L2224/85801 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06551 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/19104 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/014 ,  H01L2924/00012

Abstract: Embodiments of a flexibly-wrapped integrated circuit die device and a method for mounting a flexibly-wrapped integrated circuit die to a substrate are disclosed. In some embodiments, the flexibly-wrapped integrated circuit die device includes a substrate and a flexible integrated circuit die coupled to the substrate in a substantially vertical orientation with reference to a surface of the substrate.

Abstract translation: 公开了一种柔性包裹的集成电路管芯器件的实施例和用于将柔性封装的集成电路管芯安装到衬底的方法。 在一些实施例中，柔性包裹的集成电路管芯器件包括基板和柔性集成电路管芯，所述基板和基板相对于基板的表面以基本垂直的取向联接到基板。

公开(公告)号：US20230187300A1

公开(公告)日：2023-06-15

申请号：US17549137

申请日：2021-12-13

Applicant: Intel Corporation

Inventor： Richard Geiger ,  Georgios Panagopoulos ,  Johannes Xaver Rauh ,  Harald Gossner

IPC: H01L23/367 ,  H01L23/48 ,  H01L23/528

CPC classification number: H01L23/367 ,  H01L23/481 ,  H01L23/5286

Abstract: IC devices including BHRs and TSVs for backside heat dissipation are disclosed. An example IC device includes semiconductor structures. The IC device also includes an electrically conductive layer coupled to the semiconductor structures. The IC device further includes one or more BHRs coupled to the electrically conductive layer. Each BHR is connected to a heat dissipation plate by a TSV buried in a support structure. The heat dissipation plate is at the backside of the support structure. The BHRs, TSVs, and heat dissipation plate can conduct heat generated by the semiconductor structures to the backside of the support structure. The BHRs may also be used as power rails for delivering power to the semiconductor structures. A TSV can be enlarged to have a larger cross-sectional area than the BHR for enhancing the heat dissipation. Also, the heat dissipation plate may exceed a cell boundary for sinking heat more efficiently.

公开(公告)号：US20220320350A1

公开(公告)日：2022-10-06

申请号：US17848275

申请日：2022-06-23

Applicant: Intel Corporation

Inventor： Harald Gossner ,  Peter Baumgartner ,  Uwe Hodel ,  Domagoj Siprak ,  Stephan Leuschner ,  Richard Geiger ,  Han Wui Then ,  Marko Radosavljevic ,  Sansaptak Dasgupta

IPC: H01L29/93 ,  H01L29/06 ,  H01L29/20 ,  H01L29/778

Abstract: A variable capacitance III-N device having multiple two-dimensional electron gas (2DEG) layers are described. In some embodiments, the device comprises a first source and a first drain; a first polarization layer adjacent to the first source and the first drain; a first channel layer coupled to the first source and the first drain and adjacent to the first polarization layer, the first channel layer comprising a first 2DEG region; a second source and a second drain; a second polarization layer adjacent to the second source and the second drain; and a second channel layer coupled to the second source and the second drain and adjacent to the second polarization layer, the second channel layer comprising a second 2DEG region, wherein the second channel layer is over the first polarization layer.

公开(公告)号：US12034085B2

公开(公告)日：2024-07-09

申请号：US17848275

申请日：2022-06-23

Applicant: Intel Corporation

Inventor： Harald Gossner ,  Peter Baumgartner ,  Uwe Hodel ,  Domagoj Siprak ,  Stephan Leuschner ,  Richard Geiger ,  Han Wui Then ,  Marko Radosavljevic ,  Sansaptak Dasgupta

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/20 ,  H01L29/778 ,  H01L29/93

CPC classification number: H01L29/93 ,  H01L29/0649 ,  H01L29/2003 ,  H01L29/778

Abstract: A variable capacitance III-N device having multiple two-dimensional electron gas (2DEG) layers are described. In some embodiments, the device comprises a first source and a first drain; a first polarization layer adjacent to the first source and the first drain; a first channel layer coupled to the first source and the first drain and adjacent to the first polarization layer, the first channel layer comprising a first 2DEG region; a second source and a second drain; a second polarization layer adjacent to the second source and the second drain; and a second channel layer coupled to the second source and the second drain and adjacent to the second polarization layer, the second channel layer comprising a second 2DEG region, wherein the second channel layer is over the first polarization layer.

公开(公告)号：US20230197599A1

公开(公告)日：2023-06-22

申请号：US17554112

申请日：2021-12-17

Applicant: Intel Corporation

Inventor： Bernd Waidhas ,  Harald Gossner ,  Wolfgang Molzer ,  Georg Seidemann ,  Michael Langenbuch ,  Martin Ostermayr ,  Joachim Singer ,  Thomas Wagner ,  Klaus Herold

IPC: H01L23/522 ,  H01L21/8238 ,  H01L23/528 ,  H01L23/535 ,  H01L27/092

CPC classification number: H01L23/5226 ,  H01L21/823821 ,  H01L21/823871 ,  H01L23/5286 ,  H01L23/535 ,  H01L27/0924

Abstract: IC devices including BPRs with integrated decoupling capacitance are disclosed. An example IC device includes a first layer comprising a transistor and a support structure adjoining the first layer. The support structure includes BPRs, which are power rails buried in the support structure, and a decoupling capacitor based on the BPRs. The conductive cores of the BPRs are the electrodes of the decoupling capacitor. The dielectric barriers of the BPRs can be the dielectric of the decupling capacitor. The dielectric of the decupling capacitor may also include a dielectric element between the BPRs. Additionally or alternatively, the IC device includes another decoupling capacitor at the backside of the support structure. The other decoupling capacitor is coupled to the BPRs and can provide additional decoupling capacitance for stabilizing power supply facilitated by the BPRs.

公开(公告)号：US20230197598A1

公开(公告)日：2023-06-22

申请号：US17554004

申请日：2021-12-17

Applicant: Intel Corporation

Inventor： Georgios Panagopoulos ,  Richard Geiger ,  Peter Baumgartner ,  Harald Gossner ,  Uwe Hodel ,  Michael Langenbuch ,  Johannes Xaver Rauh ,  Alexander Bechtold ,  Richard Hudeczek ,  Carla Moran Guizan

IPC: H01L23/522 ,  H01L21/8238 ,  H01L23/528 ,  H01L23/535 ,  H01L27/092

CPC classification number: H01L23/5226 ,  H01L21/823821 ,  H01L21/823871 ,  H01L23/5286 ,  H01L23/535 ,  H01L27/0924

Abstract: IC devices including inductors or transformers formed based on BPRs are disclosed. An example IC device includes semiconductor structures of one or more transistors, an electrically conductive layer, a support structure comprising a semiconductor material, and an inductor. The inductor includes an electrical conductor constituted by a power rail buried in the support structure. The inductor also includes a magnetic core coupled to the electrical conductor. The magnetic core includes magnetic rails buried in the support structure, magnetic TSVs buried in the support structure, and a magnetic plate at the backside of the support structure. The magnetic core includes a magnetic material, such as Fe, NiFe, CoZrTa, etc. In some embodiments, the IC device includes another power rail that is buried in the support structure and constitutes another electrical conductor coupled to the magnetic core. The two power rails and magnetic core can constitute a transformer.

公开(公告)号：US11380806B2

公开(公告)日：2022-07-05

申请号：US16641222

申请日：2017-09-28

Applicant: INTEL CORPORATION

Inventor： Harald Gossner ,  Peter Baumgartner ,  Uwe Hodel ,  Domagoj Siprak ,  Stephan Leuschner ,  Richard Geiger ,  Han Wui Then ,  Marko Radosavljevic ,  Sansaptak Dasgupta

IPC: H01L29/93 ,  H01L29/06 ,  H01L29/20 ,  H01L29/778

Abstract: A variable capacitance III-N device having multiple two-dimensional electron gas (2DEG) layers are described. In some embodiments, the device comprises a first source and a first drain; a first polarization layer adjacent to the first source and the first drain; a first channel layer coupled to the first source and the first drain and adjacent to the first polarization layer, the first channel layer comprising a first 2DEG region; a second source and a second drain; a second polarization layer adjacent to the second source and the second drain; and a second channel layer coupled to the second source and the second drain and adjacent to the second polarization layer, the second channel layer comprising a second 2DEG region, wherein the second channel layer is over the first polarization layer.