公开(公告)号：US20190265771A1

公开(公告)日：2019-08-29

申请号：US15904023

申请日：2018-02-23

Applicant: Intel Corporation

Inventor： Lakshminarayana Pappu ,  Robert Milstrey ,  Amit K. Srivastava

IPC: G06F1/32 ,  G06F1/08 ,  G06F9/4401

Abstract: An apparatus is provided which comprises: a power management circuitry; and a processing circuitry comprising a processing core, wherein the power management circuitry is to: compute first voltage and frequency parameters, and transmit the first voltage and frequency parameters to the processing circuitry for operation of the processing core, and wherein in response to a detection of a fault, the power management circuitry is to: access second voltage and frequency parameters from a memory, and transmit the accessed second voltage and frequency parameters to the processing circuitry for operation of the processing core.

公开(公告)号：US09874925B2

公开(公告)日：2018-01-23

申请号：US14966708

申请日：2015-12-11

Applicant: Intel Corporation

Inventor： Sanjeev Jahagirdar ,  Varghese George ,  John B. Conrad ,  Robert Milstrey ,  Stephen A. Fischer ,  Alon Naveh ,  Shai Rotem

IPC: G06F1/32 ,  G06F12/08 ,  G06F11/14 ,  G06F12/084 ,  G06F12/0875 ,  G11C7/10 ,  G06F9/44

CPC classification number: G06F1/3287 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3246 ,  G06F1/3275 ,  G06F1/3293 ,  G06F1/3296 ,  G06F9/4418 ,  G06F11/1441 ,  G06F12/084 ,  G06F12/0875 ,  G06F2212/281 ,  G06F2212/305 ,  G06F2212/314 ,  G11C7/1072 ,  Y02B70/123 ,  Y02B70/126 ,  Y02B70/32 ,  Y02D10/152 ,  Y02D10/172 ,  Y02D50/20 ,  Y02P80/11 ,  Y10T307/305 ,  Y10T307/406 ,  Y10T307/582 ,  Y10T307/826

Abstract: Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.

公开(公告)号：US09841807B2

公开(公告)日：2017-12-12

申请号：US14959549

申请日：2015-12-04

Applicant: Intel Corporation

Inventor： Sanjeev Jahagirdar ,  Varghese George ,  John Conrad ,  Robert Milstrey ,  Stephen A. Fischer ,  Alon Naveh ,  Shai Rotem

IPC: G06F1/32 ,  G06F11/14 ,  G06F12/084 ,  G06F12/0875 ,  G11C7/10 ,  G06F9/44

CPC classification number: G06F1/3287 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3246 ,  G06F1/3275 ,  G06F1/3293 ,  G06F1/3296 ,  G06F9/4418 ,  G06F11/1441 ,  G06F12/084 ,  G06F12/0875 ,  G06F2212/281 ,  G06F2212/305 ,  G06F2212/314 ,  G11C7/1072 ,  Y02B70/123 ,  Y02B70/126 ,  Y02B70/32 ,  Y02D10/152 ,  Y02D10/172 ,  Y02D50/20 ,  Y02P80/11 ,  Y10T307/305 ,  Y10T307/406 ,  Y10T307/582 ,  Y10T307/826

Abstract: Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.

公开(公告)号：US09223390B2

公开(公告)日：2015-12-29

申请号：US14496345

申请日：2014-09-25

Applicant: Intel Corporation

Inventor： Sanjeev Jahagirdar ,  Varghese George ,  John B. Conrad ,  Robert Milstrey ,  Stephen A. Fischer ,  Alon Naveh ,  Shai Rotem

IPC: G06F1/32 ,  G06F12/08 ,  G06F11/14 ,  G11C7/10

CPC classification number: G06F1/3287 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3246 ,  G06F1/3275 ,  G06F1/3293 ,  G06F1/3296 ,  G06F9/4418 ,  G06F11/1441 ,  G06F12/084 ,  G06F12/0875 ,  G06F2212/281 ,  G06F2212/305 ,  G06F2212/314 ,  G11C7/1072 ,  Y02B70/123 ,  Y02B70/126 ,  Y02B70/32 ,  Y02D10/152 ,  Y02D10/172 ,  Y02D50/20 ,  Y02P80/11 ,  Y10T307/305 ,  Y10T307/406 ,  Y10T307/582 ,  Y10T307/826

Abstract: Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.

公开(公告)号：US20150169043A1

公开(公告)日：2015-06-18

申请号：US14630909

申请日：2015-02-25

Applicant: Intel Corporation

Inventor： Sanjeev Jahagirdar ,  Varghese George ,  John Conrad ,  Robert Milstrey ,  Stephen A. Fischer ,  Alon Naveh ,  Shai Rotem

IPC: G06F1/32

CPC classification number: G06F1/3287 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3246 ,  G06F1/3275 ,  G06F1/3293 ,  G06F1/3296 ,  G06F9/4418 ,  G06F11/1441 ,  G06F12/084 ,  G06F12/0875 ,  G06F2212/281 ,  G06F2212/305 ,  G06F2212/314 ,  G11C7/1072 ,  Y02B70/123 ,  Y02B70/126 ,  Y02B70/32 ,  Y02D10/152 ,  Y02D10/172 ,  Y02D50/20 ,  Y02P80/11 ,  Y10T307/305 ,  Y10T307/406 ,  Y10T307/582 ,  Y10T307/826

Abstract: Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.

Abstract translation: 本发明的实施例涉及一种用于零电压处理器睡眠状态的方法和装置。 处理器可以包括专用高速缓存存储器。 电压调节器可以耦合到处理器以向处理器提供工作电压。 在处理器转换到零电压电源管理状态期间，电压调节器施加到处理器的工作电压可以减小到大约零，并且与处理器相关联的状态变量可以被保存到专用高速缓冲存储器。

公开(公告)号：US20150058667A1

公开(公告)日：2015-02-26

申请号：US14496345

申请日：2014-09-25

Applicant: Intel Corporation

Inventor： Sanjeev Jahagirdar ,  Varghese George ,  John B. Conrad ,  Robert Milstrey ,  Stephen A. Fischer ,  Alon Naveh ,  Shai Rotem

IPC: G06F1/32 ,  G11C7/10 ,  G06F12/08 ,  G06F11/14

CPC classification number: G06F1/3287 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3246 ,  G06F1/3275 ,  G06F1/3293 ,  G06F1/3296 ,  G06F9/4418 ,  G06F11/1441 ,  G06F12/084 ,  G06F12/0875 ,  G06F2212/281 ,  G06F2212/305 ,  G06F2212/314 ,  G11C7/1072 ,  Y02B70/123 ,  Y02B70/126 ,  Y02B70/32 ,  Y02D10/152 ,  Y02D10/172 ,  Y02D50/20 ,  Y02P80/11 ,  Y10T307/305 ,  Y10T307/406 ,  Y10T307/582 ,  Y10T307/826

Abstract: Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.

公开(公告)号：US20220075400A1

公开(公告)日：2022-03-10

申请号：US17528241

申请日：2021-11-17

Applicant: Intel Corporation

Inventor： Sriram R. Vangal ,  Jayanth Mallanayakanahalli Devaraju ,  Vivek De ,  Robert Milstrey ,  Stephen H. Gunther

IPC: G05F1/46 ,  G06F16/901 ,  G06F1/3203 ,  G06F1/28

Abstract: In one embodiment, a processor includes a minimum energy point (MEP) controller to: generate a change in thermal tracking information, based at least in part on prior and current thermal information; generate a change in activity tracking information, based at least in part on prior activity information and current activity information; and determine a MEP performance state based at least in part on the change in thermal tracking information and the change in activity tracking information. Other embodiments are described and claimed.

公开(公告)号：US11231731B2

公开(公告)日：2022-01-25

申请号：US16455929

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： Sriram R. Vangal ,  Jayanth Mallanayakanahalli Devaraju ,  Vivek De ,  Robert Milstrey ,  Stephen H. Gunther

IPC: G06F1/3203 ,  G06F1/28 ,  G05F1/46 ,  G06F16/901 ,  G06F16/90

Abstract: In one embodiment, a processor includes a minimum energy point (MEP) controller to: generate a change in thermal tracking information, based at least in part on prior and current thermal information; generate a change in activity tracking information, based at least in part on prior activity information and current activity information; and determine a MEP performance state based at least in part on the change in thermal tracking information and the change in activity tracking information. Other embodiments are described and claimed.

公开(公告)号：US20170269672A9

公开(公告)日：2017-09-21

申请号：US14966708

申请日：2015-12-11

Applicant: Intel Corporation

Inventor： Sanjeev Jahagirdar ,  Varghese George ,  John B. Conrad ,  Robert Milstrey ,  Stephen A. Fischer ,  Alon Naveh ,  Shai Rotem

IPC: G06F1/32 ,  G06F12/08

CPC classification number: G06F1/3287 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3246 ,  G06F1/3275 ,  G06F1/3293 ,  G06F1/3296 ,  G06F9/4418 ,  G06F11/1441 ,  G06F12/084 ,  G06F12/0875 ,  G06F2212/281 ,  G06F2212/305 ,  G06F2212/314 ,  G11C7/1072 ,  Y02B70/123 ,  Y02B70/126 ,  Y02B70/32 ,  Y02D10/152 ,  Y02D10/172 ,  Y02D50/20 ,  Y02P80/11 ,  Y10T307/305 ,  Y10T307/406 ,  Y10T307/582 ,  Y10T307/826

Abstract: Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.

公开(公告)号：US20160091958A1

公开(公告)日：2016-03-31

申请号：US14959549

申请日：2015-12-04

Applicant: Intel Corporation

Inventor： Sanjeev Jahagirdar ,  Varghese George ,  John Conrad ,  Robert Milstrey ,  Stephen A. Fischer ,  Alon Naveh ,  Shai Rotem

IPC: G06F1/32

CPC classification number: G06F1/3287 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3246 ,  G06F1/3275 ,  G06F1/3293 ,  G06F1/3296 ,  G06F9/4418 ,  G06F11/1441 ,  G06F12/084 ,  G06F12/0875 ,  G06F2212/281 ,  G06F2212/305 ,  G06F2212/314 ,  G11C7/1072 ,  Y02B70/123 ,  Y02B70/126 ,  Y02B70/32 ,  Y02D10/152 ,  Y02D10/172 ,  Y02D50/20 ,  Y02P80/11 ,  Y10T307/305 ,  Y10T307/406 ,  Y10T307/582 ,  Y10T307/826

Abstract: Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.