公开(公告)号：US20240105718A1

公开(公告)日：2024-03-28

申请号：US17934251

申请日：2022-09-22

Applicant: Intel Corporation

Inventor： Tao Chu ,  Guowei Xu ,  Minwoo Jang ,  Yanbin Luo ,  Feng Zhang ,  Ting-Hsiang Hung ,  Chia-Ching Lin

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/08 ,  H01L29/778 ,  H01L29/786

CPC classification number: H01L27/0886 ,  H01L21/823412 ,  H01L21/823418 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/778 ,  H01L29/78696

Abstract: Methods for fabricating an integrated circuit (IC) device with a protection liner between doped semiconductor regions are provided. An example IC device includes a channel material having a first face and a second face opposite the first face, a first doped region and a second doped region in the channel material, extending from the second face towards the first face by a first distance; and an insulator structure in a portion of the channel material between the first and second doped regions, the insulator structure extending from the second face towards the first face by a second distance greater than the first distance. The insulator structure includes a first portion between the second face and the first distance and a second portion between first distance and the second distance. The insulator structure includes a liner material on sidewalls of the first portion but absent on sidewalls of the second portion.

公开(公告)号：US20250096114A1

公开(公告)日：2025-03-20

申请号：US18469810

申请日：2023-09-19

Applicant: Intel Corporation

Inventor： Robin Chao ,  Chiao-Ti Huang ,  Guowei Xu ,  Ting-Hsiang Hung ,  Tao Chu ,  Feng Zhang ,  Chia-Ching Lin ,  Yang Zhang ,  Anand Murthy ,  Conor P. Puls

IPC: H01L23/522 ,  H01L23/528

Abstract: Techniques to form semiconductor devices can include one or more via structures having substrate taps. A semiconductor device includes a gate structure around or otherwise on a semiconductor region (or channel region). The gate structure may extend over the semiconductor regions of any number of devices along a given direction. The gate structure may be interrupted, for example, between two transistors with a via structure that extends through an entire thickness of the gate structure and includes a conductive core. The via structure has a conductive foot portion beneath the gate structure and a conductive arm portion extending from the conductive foot portion along a height of the gate structure. The conductive foot portion has a greater width along the given direction than any part of the conductive arm portion. The via structure may further include one or more dielectric layers between the conductive arm portion and the gate structure.

公开(公告)号：US20240321962A1

公开(公告)日：2024-09-26

申请号：US18187965

申请日：2023-03-22

Applicant: Intel Corporation

Inventor： Tao Chu ,  Robin Chao ,  Guowei Xu ,  Feng Zhang ,  Minwoo Jang

IPC: H01L29/06 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/775

CPC classification number: H01L29/068 ,  H01L21/823807 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/775 ,  H01L29/165 ,  H01L29/42392

Abstract: Described herein are nanoribbon-based transistor devices in which the nanoribbons have rounded cross-sections. The nanoribbons may include caps or outer layers of semiconductor channel material grown over an inner layer of semiconductor channel material. Different materials may be used for the outer layers of NMOS and PMOS transistors. In one example, an integrated circuit device includes NMOS transistors formed from or more nanoribbons with rounded cross-sections and an outer layer of silicon, and a PMOS transistors formed from or more nanoribbons with rounded cross-sections and an outer layer of silicon germanium.

公开(公告)号：US20250006734A1

公开(公告)日：2025-01-02

申请号：US18216493

申请日：2023-06-29

Applicant: Intel Corporation

Inventor： Tao Chu ,  Minwoo Jang ,  Yanbin Luo ,  Paul Packan ,  Guowei Xu ,  Chiao-Ti Huang ,  Robin Chao ,  Feng Zhang ,  Ting-Hsiang Hung ,  Chia-Ching Lin ,  Yang Zhang ,  Chung-Hsun Lin

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/775 ,  H01L29/78

Abstract: An integrated circuit (IC) device includes a stripe of material perpendicular to, and spanning between, semiconductor structures with multiple widths, and the stripe is between transistors with channel regions of differing widths in the semiconductor structures. The material stripes cover transition portions between different widths of the semiconductor structures. The semiconductor structures may be channel structures of different types, including groups of fins or nanoribbons. Channel regions of differing widths may include more or fewer fins or narrower or wider nanoribbons. The channel regions may have alternating conductivity types, n- and p-type.

公开(公告)号：US20240290788A1

公开(公告)日：2024-08-29

申请号：US18175591

申请日：2023-02-28

Applicant: Intel Corporation

Inventor： Guowei Xu ,  Tao Chu ,  Chiao-Ti Huang ,  Robin Chao ,  David Towner ,  Orb Acton ,  Omair Saadat ,  Feng Zhang ,  Dax M. Crum ,  Yang Zhang ,  Biswajeet Guha ,  Oleg Golonzka ,  Anand S. Murthy

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/778 ,  H01L29/786

CPC classification number: H01L27/0924 ,  H01L21/823807 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/778 ,  H01L29/78696

Abstract: A metal gate fabrication method for nanoribbon-based transistors and associated transistor arrangements, IC structures, and devices are disclosed. An example IC structure fabricated using metal gate fabrication method described herein may include a first stack of N-type nanoribbons, a second stack of P-type nanoribbons, a first gate region enclosing portions of the nanoribbons of the first stack and including an NWF material between adjacent nanoribbons of the first stack, and a second gate region enclosing portions of the nanoribbons of the second stack and including a PWF material between adjacent nanoribbons of the second stack, where the second gate region includes the PWF material at sidewalls of the nanoribbons of the second stack and further includes the NWF material so that the PWF material is between the sidewalls of the nanoribbons of the second stack and the NWF material.

公开(公告)号：US20240088265A1

公开(公告)日：2024-03-14

申请号：US17940194

申请日：2022-09-08

Applicant: Intel Corporation

Inventor： Tao Chu ,  Guowei Xu ,  Feng Zhang ,  Ting-Hsiang Hung ,  Chia-Ching Lin

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/786

CPC classification number: H01L29/6656 ,  H01L29/0669 ,  H01L29/78618

Abstract: Techniques are provided herein to form semiconductor devices having epitaxial growth laterally extending between inner spacer structures to mitigate issues caused by the inner spacer structures either being too thick or too thin. A directional etch is performed along the side of a multilayer fin to create a relatively narrow opening for a source or drain region to increase the usable fin space for forming the inner spacer structures. After the inner spacer structures are formed around ends of the semiconductor layers within the fin, the exposed ends of the semiconductor layers are laterally recessed inwards from the outermost sidewalls of the inner spacer structures. Accordingly, the epitaxial source or drain region is grown from the recessed semiconductor ends and thus fills in the recessed regions between the spacer structures.

公开(公告)号：US20250107156A1

公开(公告)日：2025-03-27

申请号：US18471710

申请日：2023-09-21

Applicant: Intel Corporation

Inventor： Chiao-Ti Huang ,  Robin Chao ,  Jaladhi Mehta ,  Tao Chu ,  Guowei Xu ,  Ting-Hsiang Hung ,  Feng Zhang ,  Yang Zhang ,  Chia-Ching Lin ,  Chung-Hsun Lin ,  Anand Murthy

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66

Abstract: Techniques are provided herein to form an integrated circuit having dielectric material formed in cavities beneath source or drain regions. The cavities may be formed within subfin portions of semiconductor devices. In one such example, a FET (field effect transistor) includes a gate structure extending around a fin or any number of nanowires of semiconductor material. The semiconductor material may extend in a first direction between source and drain regions while the gate structure extends over the semiconductor material in a second direction substantially orthogonal to the first direction. A dielectric fill may be formed in a recess beneath the source or drain regions, or a dielectric liner may be formed on sidewalls of the recess, to prevent epitaxial growth of the source or drain regions from the subfins. Removal of the semiconductor subfin from the backside may then be performed without causing damage to the source or drain regions.

公开(公告)号：US20250089310A1

公开(公告)日：2025-03-13

申请号：US18466246

申请日：2023-09-13

Applicant: Intel Corporation

Inventor： Ting-Hsiang Hung ,  Yang Zhang ,  Robin Chao ,  Guowei Xu ,  Tao Chu ,  Chiao-Ti Huang ,  Feng Zhang ,  Chia-Ching Lin ,  Anand Murthy

IPC: H01L29/06 ,  H01L27/092 ,  H01L29/423 ,  H01L29/778 ,  H01L29/786

Abstract: Techniques are provided to form semiconductor devices that include through-gate structures (e.g., gate cut structures or conductive via structures) that have an airgap spacer between the structure and the adjacent gate electrode. In an example, a semiconductor device includes a gate structure around or otherwise on a semiconductor region (or channel region) that extends from a first source or drain region to a second source or drain region. A through-gate structure may extend in a third direction through an entire thickness of the gate structure and adjacent to the semiconductor region along the second direction. The through-gate structure may be a dielectric structure (e.g., a gate cut) or a conductive structure (e.g., a via). In either case, an airgap spacer exists between the through-gate structure and the gate structure.

公开(公告)号：US20240321987A1

公开(公告)日：2024-09-26

申请号：US18187990

申请日：2023-03-22

Applicant: Intel Corporation

Inventor： Tao Chu ,  Guowei Xu ,  Robin Chao ,  Chiao-Ti Huang ,  Feng Zhang ,  Minwoo Jang ,  Chia-Ching Lin ,  Biswajeet Guha ,  Yue Zhong ,  Anand S. Murthy

IPC: H01L29/423 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L27/0886 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

Abstract: Described herein are integrated circuit devices that include both nanoribbon-based transistors and fin-shaped transistors. The nanoribbon transistors may have shorter channel lengths than the fin transistors. In addition, the nanoribbon transistors may have thinner gate dielectrics than the fin transistors.