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    VIA STRUCTURE WITH IMPROVED SUBSTRATE GROUNDING
    1.
    发明申请
    VIA STRUCTURE WITH IMPROVED SUBSTRATE GROUNDING 有权

    公开(公告)号：US20250096114A1

    公开(公告)日：2025-03-20

    申请号：US18469810

    申请日：2023-09-19

    Applicant: Intel Corporation

    Inventor： Robin Chao ,  Chiao-Ti Huang ,  Guowei Xu ,  Ting-Hsiang Hung ,  Tao Chu ,  Feng Zhang ,  Chia-Ching Lin ,  Yang Zhang ,  Anand Murthy ,  Conor P. Puls

    IPC: H01L23/522 ,  H01L23/528

    Abstract: Techniques to form semiconductor devices can include one or more via structures having substrate taps. A semiconductor device includes a gate structure around or otherwise on a semiconductor region (or channel region). The gate structure may extend over the semiconductor regions of any number of devices along a given direction. The gate structure may be interrupted, for example, between two transistors with a via structure that extends through an entire thickness of the gate structure and includes a conductive core. The via structure has a conductive foot portion beneath the gate structure and a conductive arm portion extending from the conductive foot portion along a height of the gate structure. The conductive foot portion has a greater width along the given direction than any part of the conductive arm portion. The via structure may further include one or more dielectric layers between the conductive arm portion and the gate structure.

    EPITAXIAL REGIONS EXTENDING BETWEEN INNER GATE SPACERS
    3.
    发明公开
    EPITAXIAL REGIONS EXTENDING BETWEEN INNER GATE SPACERS 审中-公开

    公开(公告)号：US20240088265A1

    公开(公告)日：2024-03-14

    申请号：US17940194

    申请日：2022-09-08

    Applicant: Intel Corporation

    Inventor： Tao Chu ,  Guowei Xu ,  Feng Zhang ,  Ting-Hsiang Hung ,  Chia-Ching Lin

    IPC: H01L29/66 ,  H01L29/06 ,  H01L29/786

    CPC classification number: H01L29/6656 ,  H01L29/0669 ,  H01L29/78618

    Abstract: Techniques are provided herein to form semiconductor devices having epitaxial growth laterally extending between inner spacer structures to mitigate issues caused by the inner spacer structures either being too thick or too thin. A directional etch is performed along the side of a multilayer fin to create a relatively narrow opening for a source or drain region to increase the usable fin space for forming the inner spacer structures. After the inner spacer structures are formed around ends of the semiconductor layers within the fin, the exposed ends of the semiconductor layers are laterally recessed inwards from the outermost sidewalls of the inner spacer structures. Accordingly, the epitaxial source or drain region is grown from the recessed semiconductor ends and thus fills in the recessed regions between the spacer structures.

    LATERAL ETCHING PROCESS TO REMOVE METAL GATE FOOT STRUCTURES
    6.
    发明申请
    LATERAL ETCHING PROCESS TO REMOVE METAL GATE FOOT STRUCTURES 有权

    公开(公告)号：US20250087530A1

    公开(公告)日：2025-03-13

    申请号：US18463436

    申请日：2023-09-08

    Applicant: Intel Corporation

    Inventor： Chiao-Ti Huang ,  Tao Chu ,  Guowei Xu ,  Robin Chao ,  Feng Zhang ,  Yang Zhang ,  Ting-Hsiang Hung ,  Anand Murthy

    IPC: H01L21/762 ,  H01L21/768 ,  H01L23/48 ,  H01L27/088 ,  H01L27/12

    Abstract: Techniques are provided to form semiconductor devices where portions of the gate structure (e.g., foot structures) adjacent to the subfins have been removed. A semiconductor device includes a gate structure around or otherwise on a semiconductor region. The gate structure includes a gate dielectric and a gate electrode. The gate structure may be interrupted, for example, between two transistors with a gate cut that extends through an entire thickness of the gate structure and includes dielectric material to electrically isolate the portions of the gate structure on either side of the gate cut. The gate cut includes dielectric lobe structures that extend outwards from the sidewalls of the gate cut. The lobe structures effectively replace foot structures of the gate structure between the gate cut and subfin portions of the semiconductor fins. Removing the gate foot structures contributes to the reduction of the parasitic capacitance in the semiconductor device.

    BARRIER LAYER FOR DIELECTRIC RECESS MITIGATION
    8.
    发明公开
    BARRIER LAYER FOR DIELECTRIC RECESS MITIGATION 审中-公开

    公开(公告)号：US20240088217A1

    公开(公告)日：2024-03-14

    申请号：US17940195

    申请日：2022-09-08

    Applicant: Intel Corporation

    Inventor： Tao Chu ,  Minwoo Jang ,  Chia-Ching Lin ,  Yanbin Luo ,  Ting-Hsiang Hung ,  Feng Zhang ,  Guowei Xu

    IPC: H01L29/06 ,  H01L21/762 ,  H01L29/78

    CPC classification number: H01L29/0649 ,  H01L21/76224 ,  H01L29/7856

    Abstract: Techniques are provided herein to form semiconductor devices that include a layer across an upper surface of a dielectric fill between devices and configured to prevent or otherwise reduce recessing of the dielectric fill. In this manner, the layer may be referred to as a barrier layer or recess-inhibiting layer. The semiconductor regions of the devices extend above a subfin region that may be native to the substrate. These subfin regions are separated from one another using a dielectric fill that acts as a shallow trench isolation (STI) structure to electrically isolate devices from one another. A barrier layer is formed over the dielectric fill early in the fabrication process to prevent or otherwise reduce the dielectric fill from recessing during subsequent processing. The layer may include oxygen and a metal, such as aluminum.

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