公开(公告)号：US10088728B2

公开(公告)日：2018-10-02

申请号：US15662385

申请日：2017-07-28

Applicant: Japan Display Inc.

Inventor： Yohei Yamaguchi ,  Arichika Ishida ,  Hidekazu Miyake ,  Hiroto Miyake ,  Isao Suzumura

IPC: G02F1/1362 ,  H01L29/786 ,  H01L27/12 ,  G02F1/1368 ,  G02F1/1343 ,  H01L29/423

Abstract: According to one embodiment, a display device includes an insulating substrate, a thin-film transistor including a semiconductor layer formed on a layer above the insulating substrate, a gate electrode which at least partly overlaps the semiconductor layer, and a first electrode and a second electrode which are electrically connected to the semiconductor layer, and a light shielding layer formed between the thin-film transistor and the insulating substrate to at least partly overlap the semiconductor layer, the light shielding layer electrically connected to the gate electrode.

公开(公告)号：US09964824B2

公开(公告)日：2018-05-08

申请号：US14793106

申请日：2015-07-07

Applicant: Japan Display Inc.

Inventor： Isao Suzumura ,  Arichika Ishida ,  Norihiro Uemura ,  Hidekazu Miyake ,  Hiroto Miyake ,  Yohei Yamaguchi

IPC: G09G3/36 ,  G02F1/1368 ,  G02F1/1333 ,  G02F1/1362 ,  H01L27/12

CPC classification number: G02F1/1368 ,  G02F1/133345 ,  G02F1/136227 ,  H01L27/1288

Abstract: According to one embodiment, a display device includes a TFT on an insulating substrate. The TFT includes a gate electrode, an insulating layer on the gate electrode, a semiconductor layer on the insulating layer, and a source electrode and a drain electrode each provided in contact with at least a part of the semiconductor layer. The source and drain electrodes have a laminated structure including a lower layer, an intermediate layer and an upper layer. The source and drain electrodes include sidewalls each including a first tapered portion on the upper layer side, a second tapered portion on the lower layer side and a sidewall protective film attached to the second tapered portion. The taper angle of the first tapered portion is smaller than that of the second tapered portion.

公开(公告)号：US09337322B2

公开(公告)日：2016-05-10

申请号：US14729117

申请日：2015-06-03

Applicant: Japan Display Inc.

Inventor： Masato Hiramatsu ,  Masayoshi Fuchi ,  Arichika Ishida

IPC: H01L29/66 ,  H01L29/786 ,  H01L29/49 ,  H01L21/02 ,  H01L21/465

CPC classification number: H01L29/7869 ,  H01L21/02164 ,  H01L21/02211 ,  H01L21/02214 ,  H01L21/02271 ,  H01L21/02565 ,  H01L21/0262 ,  H01L21/443 ,  H01L21/465 ,  H01L29/24 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/78696

Abstract: According to one embodiment, a thin-film transistor comprises an oxide semiconductor layer formed on a part of a substrate, a first gate insulator film of a silicon dioxide film formed on the oxide semiconductor layer and by the CVD method with a silane-based source gas, a second gate insulator film of a silicon dioxide film formed on the first gate insulator film by the CVD method with a TEOS source gas, and a gate electrode formed on the second gate insulator film.

Abstract translation: 根据一个实施例，薄膜晶体管包括形成在衬底的一部分上的氧化物半导体层，形成在氧化物半导体层上的二氧化硅膜的第一栅极绝缘膜和通过CVD法的硅烷基源 气体，通过CVD法用TEOS源气体形成在第一栅极绝缘膜上的二氧化硅膜的第二栅极绝缘膜，以及形成在第二栅极绝缘膜上的栅电极。

公开(公告)号：US12271088B2

公开(公告)日：2025-04-08

申请号：US18428228

申请日：2024-01-31

Applicant: Japan Display Inc.

Inventor： Yohei Yamaguchi ,  Arichika Ishida ,  Hidekazu Miyake ,  Hiroto Miyake ,  Isao Suzumura

IPC: G02F1/1368 ,  G02F1/1343 ,  G02F1/1362 ,  H01L27/12 ,  H01L29/423 ,  H01L29/786

Abstract: According to one embodiment, a semiconductor device includes an insulating substrate, a first metal layer on the insulating substrate, a first insulating layer on the insulating substrate and the first metal layer, a semiconductor layer on the first insulating layer, a second insulating layer on the semiconductor layer and the first insulating layer, a second metal layer on the second insulating layer, and a first electrode and a second electrode which are electrically connected to the semiconductor layer. The first metal layer overlaps the second metal layer. A third metal layer contacts a top surface of the second metal layer and a top surface of the first metal layer.

公开(公告)号：US10976580B2

公开(公告)日：2021-04-13

申请号：US16533903

申请日：2019-08-07

Applicant: Japan Display Inc.

Inventor： Arichika Ishida ,  Yasushi Kawata

IPC: G02F1/1333 ,  H01L51/00

Abstract: According to one embodiment, a display device includes a first substrate including a first resin substrate having a first thermal expansion coefficient, and a first barrier layer having a second thermal expansion coefficient which is lower than the first thermal expansion coefficient, a second substrate including a second resin substrate having a third thermal expansion coefficient which is equal to the first thermal expansion coefficient, and a second barrier layer having a fourth thermal expansion coefficient which is lower than the third thermal expansion coefficient and is equal to the first thermal expansion coefficient, and a display element located between the first resin substrate and the second resin substrate.

公开(公告)号：US10658400B2

公开(公告)日：2020-05-19

申请号：US15479305

申请日：2017-04-05

Applicant: Japan Display Inc.

Inventor： Masato Hiramatsu ,  Yasushi Kawata ,  Arichika Ishida

IPC: H01L27/12 ,  H01L29/04 ,  H01L29/16 ,  H01L29/66 ,  H01L29/786

Abstract: According to one embodiment, a display device includes an underlying insulation layer formed on a surface of a resin layer, and a thin-film transistor formed above the surface of the resin layer via the underlying insulation layer. The underlying insulation layer includes a three-layer multilayer structure of a first silicon oxide film, a silicon nitride film formed above the first silicon oxide film, and a second silicon oxide film formed above the silicon nitride film.

公开(公告)号：US10276601B2

公开(公告)日：2019-04-30

申请号：US15682594

申请日：2017-08-22

Applicant: Japan Display Inc.

Inventor： Noriyoshi Kanda ,  Arichika Ishida ,  Masayoshi Fuchi

IPC: H01L27/12 ,  H01L51/00 ,  H01L51/50

Abstract: According to one embodiment, a display device includes an insulating substrate, a first transistor including a first semiconductor layer of silicon and a first electrode, a first insulating layer provided above the first semiconductor layer, a second transistor including a second semiconductor layer of an oxide semiconductor, a second electrode and a conductive layer electrically connected to the second semiconductor layer, and a second insulating layer provided above the first insulating layer and the second semiconductor layer, the first electrode being electrically connected to the first semiconductor layer in a first hole, and the second electrode being in contact with the conductive layer in a second hole.

公开(公告)号：US20180061857A1

公开(公告)日：2018-03-01

申请号：US15682594

申请日：2017-08-22

Applicant: Japan Display Inc.

Inventor： Noriyoshi KANDA ,  Arichika Ishida ,  Masayoshi Fuchi

IPC: H01L27/12 ,  H01L51/00 ,  H01L51/50

CPC classification number: H01L27/124 ,  H01L27/1203 ,  H01L27/1225 ,  H01L27/1251 ,  H01L29/78633 ,  H01L29/7869 ,  H01L29/78696 ,  H01L51/0002 ,  H01L51/0094 ,  H01L51/5012

Abstract: According to one embodiment, a display device includes an insulating substrate, a first transistor including a first semiconductor layer of silicon and a first electrode, a first insulating layer provided above the first semiconductor layer, a second transistor including a second semiconductor layer of an oxide semiconductor, a second electrode and a conductive layer electrically connected to the second semiconductor layer, and a second insulating layer provided above the first insulating layer and the second semiconductor layer, the first electrode being electrically connected to the first semiconductor layer in a first hole, and the second electrode being in contact with the conductive layer in a second hole.

公开(公告)号：US09660039B2

公开(公告)日：2017-05-23

申请号：US15062887

申请日：2016-03-07

Applicant: Japan Display Inc.

Inventor： Hidekazu Miyake ,  Arichika Ishida ,  Hiroto Miyake ,  Isao Suzumura ,  Yohei Yamaguchi

IPC: H01L29/49 ,  H01L29/417 ,  H01L29/786

CPC classification number: H01L29/41733 ,  H01L29/78696

Abstract: According to one embodiment, a thin-film transistor includes a semiconductor layer SC including a channel region, and a source region and a drain region on both sides of the channel region, a gate electrode GE, a first electrode SE connected to the source region via a first contact hole CH1, a second electrode DE connected to the drain region via a second contact hole CH2, a source line connected to the first electrode, and a drain line connected to the second electrode. A distance from the first and second contact holes to an end of the respective regions in a direction of a channel width is greater than or equal to 5 μm and less than or equal to 30 μm. The source line and the drain line extend in directions different from each other.

公开(公告)号：US09613860B2

公开(公告)日：2017-04-04

申请号：US14996323

申请日：2016-01-15

Applicant: Japan Display Inc.

Inventor： Isao Suzumura ,  Arichika Ishida ,  Hidekazu Miyake ,  Hiroto Miyake ,  Yohei Yamaguchi

IPC: H01L21/768 ,  H01L29/66 ,  H01L21/02 ,  H01L29/417 ,  H01L29/45 ,  H01L29/786 ,  H01L29/49 ,  H01L21/78

CPC classification number: H01L21/76895 ,  H01L21/022 ,  H01L21/32136 ,  H01L21/465 ,  H01L21/78 ,  H01L29/41733 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/7869

Abstract: According to one embodiment, a method of manufacturing a thin-film transistor includes forming a semiconductor layer on a gate electrode with an insulating layer 12 being interposed, forming interconnect formation layers on the semiconductor layer, forming a plurality of interconnects and electrodes by patterning the interconnect formation layers through etching, patterning the semiconductor layer in an island shape through etching after forming the electrodes, exposing a channel region of the semiconductor layer by etching a part of the electrodes on the semiconductor layer, and forming a protective layer so as to overlap the interconnects, the electrodes and the semiconductor layer having the island shape.