公开(公告)号：US20200349247A1

公开(公告)日：2020-11-05

申请号：US16864902

申请日：2020-05-01

申请人： Jae-sun Seo ,  Shihui Yin ,  Sai Kiran Cherupally

发明人： Jae-sun Seo ,  Shihui Yin ,  Sai Kiran Cherupally

IPC分类号： G06F21/32 ,  H04L9/32 ,  H04L9/08 ,  G06N3/08 ,  A61B5/00

摘要： A smart hardware security engine using biometric features and hardware-specific features is provided. The smart security engine can combine one or more entropy sources, including individually distinguishable biometric features, and hardware-specific features to perform secret key generation for user registration and authentication. Such hybrid signatures may be distinct from person-to-person (e.g., due to the biometric features) and from device-to-device (e.g., due to the hardware-specific features) while varying over time. Thus, embodiments described herein can be used for personal device authentication as well as secret random key generation, significantly reducing the scope of an attack.

公开(公告)号：US10706923B2

公开(公告)日：2020-07-07

申请号：US16126563

申请日：2018-09-10

申请人： Jae-sun Seo ,  Shimeng Yu

发明人： Jae-sun Seo ,  Shimeng Yu

IPC分类号： G11C13/00 ,  G06N3/02 ,  G11C7/18 ,  G11C11/54 ,  G11C7/10

摘要： A resistive random-access memory (RRAM) system includes an RRAM cell. The RRAM cell includes a first select line and a second select line, a word line, a bit line, a first resistive memory device, a first switching device, a second resistive memory device, a second switching device, and a comparator. The first resistive memory device is coupled between a first access node and the bit line. The first switching device is coupled between the first select line and the first access node. The second resistive memory device is coupled between a second access node and the bit line. The second switching device is coupled between the second select line and the second access node. The comparator includes a first input coupled to the bit line, a second input, and an output.

公开(公告)号：US20190244100A1

公开(公告)日：2019-08-08

申请号：US16335775

申请日：2017-09-21

申请人： Jae-sun SEO ,  Minkyu KIM ,  ARIZONA BOARD OF REGENTS ON BEHALF OF ARIZONA STATE UNIVERSITY

发明人： Jae-sun Seo ,  Minkyu Kim

IPC分类号： G06N3/08 ,  G06F7/48

CPC分类号： G06N3/08 ,  G06F7/48 ,  G06N3/0454

摘要： Techniques are described for efficiently reducing the amount of total computation in convolutional neural networks (CNNs) without affecting the output result or classification accuracy. Computation redundancy in CNNs is reduced by exploiting the computing nature of the convolution and subsequent pooling (e.g., sub-sampling) operations. In some implementations, the input features may be divided into a group of precision values and the operation(s) may be cascaded. A maximum may be identified (e.g., by 90% probability) using a small number of bits in the input features, and the full-precision convolution may then be performed on the maximum input. Accordingly, the total number of bits used to perform the convolution is reduced without affecting the output features or the final classification accuracy.

公开(公告)号：US20190080755A1

公开(公告)日：2019-03-14

申请号：US16126563

申请日：2018-09-10

申请人： Jae-sun Seo ,  Shimeng Yu

发明人： Jae-sun Seo ,  Shimeng Yu

IPC分类号： G11C13/00 ,  G11C7/18 ,  G06N3/02

摘要： A resistive random-access memory (RRAM) system includes an RRAM cell. The RRAM cell includes a first select line and a second select line, a word line, a bit line, a first resistive memory device, a first switching device, a second resistive memory device, a second switching device, and a comparator. The first resistive memory device is coupled between a first access node and the bit line. The first switching device is coupled between the first select line and the first access node. The second resistive memory device is coupled between a second access node and the bit line. The second switching device is coupled between the second select line and the second access node. The comparator includes a first input coupled to the bit line, a second input, and an output.

公开(公告)号：US09466362B2

公开(公告)日：2016-10-11

申请号：US14824782

申请日：2015-08-12

申请人： Shimeng Yu ,  Yu Cao ,  Jae-sun Seo ,  Sarma Vrudhula ,  Jieping Ye

发明人： Shimeng Yu ,  Yu Cao ,  Jae-sun Seo ,  Sarma Vrudhula ,  Jieping Ye

IPC分类号： G11C5/06 ,  G11C13/00

CPC分类号： G11C13/0026 ,  G11C5/06 ,  G11C13/0002 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C2213/74 ,  G11C2213/77 ,  G11C2213/79

摘要： This disclosure relates generally to resistive memory systems. The resistive memory systems may be utilized to implement neuro-inspired learning algorithms with full parallelism. In one embodiment, a resistive memory system includes a cross point resistive network and switchable paths. The cross point resistive network includes variable resistive elements and conductive lines. The conductive lines are coupled to the variable resistive elements such that the conductive lines and the variable resistive elements form the cross point resistive network. The switchable paths are connected to the conductive lines so that the switchable paths are operable to selectively interconnect groups of the conductive lines such that subsets of the variable resistive elements each provide a combined variable conductance. With multiple resistive elements in the subsets, process variations in the conductances of the resistive elements average out. As such, learning algorithms may be implemented with greater precision using the cross point resistive network.

摘要翻译： 本公开一般涉及电阻式存储器系统。 电阻式存储器系统可用于实现具有完全并行性的神经启发式学习算法。 在一个实施例中，电阻式存储器系统包括交叉点电阻网络和可切换路径。 交叉点电阻网络包括可变电阻元件和导线。 导线耦合到可变电阻元件，使得导线和可变电阻元件形成交叉电阻网络。 可切换路径连接到导线，使得可切换路径可操作以选择性地互连导电线组，使得可变电阻元件的子集各自提供组合的可变电导。 在子集中具有多个电阻元件，电阻元件的电导的工艺变化平均。 因此，可以使用交叉点电阻网络以更高的精度来实现学习算法。

公开(公告)号：US20120259804A1

公开(公告)日：2012-10-11

申请号：US13083414

申请日：2011-04-08

申请人： Bernard V. Brezzo ,  Leland Chang ,  Steven K. Esser ,  Daniel J. Friedman ,  Yong Liu ,  Dharmendra S. Modha ,  Robert K. Montoye ,  Bipin Rajendran ,  Jae-sun Seo ,  Jose A. Tierno

发明人： Bernard V. Brezzo ,  Leland Chang ,  Steven K. Esser ,  Daniel J. Friedman ,  Yong Liu ,  Dharmendra S. Modha ,  Robert K. Montoye ,  Bipin Rajendran ,  Jae-sun Seo ,  Jose A. Tierno

IPC分类号： G06N3/04 ,  G06N3/08

CPC分类号： G06N3/063 ,  G06N3/04 ,  G06N3/049 ,  G06N3/082

摘要： A reconfigurable neural network circuit is provided. The reconfigurable neural network circuit comprises an electronic synapse array including multiple synapses interconnecting a plurality of digital electronic neurons. Each neuron comprises an integrator that integrates input spikes and generates a signal when the integrated inputs exceed a threshold. The circuit further comprises a control module for reconfiguring the synapse array. The control module comprises a global final state machine that controls timing for operation of the circuit, and a priority encoder that allows spiking neurons to sequentially access the synapse array.

公开(公告)号：US08242811B2

公开(公告)日：2012-08-14

申请号：US12758189

申请日：2010-04-12

申请人： Jae-sun Seo ,  Ronald Ho ,  Robert J. Drost ,  Robert D. Hopkins

发明人： Jae-sun Seo ,  Ronald Ho ,  Robert J. Drost ,  Robert D. Hopkins

IPC分类号： H03K3/00

CPC分类号： G06F13/4072 ,  G06F2213/0038 ,  H03K3/3565 ,  Y02D10/14 ,  Y02D10/151

摘要： Some embodiments of the present invention provide techniques and systems for high-bandwidth on-chip communication. During operation, the system receives an input voltage signal which is to be transmitted over a wire in a chip. The system then generates one or more modified voltage signals from the input voltage signal. Next, the system drives each of the voltage signals (i.e., the input voltage signal and the one or more modified voltage signals) through a respective capacitor. The system then combines the output signals from the capacitors to obtain a combined voltage signal. Next, the system transmits the combined voltage signal over the wire. The transmitted signals can then be received by a hysteresis receiver which is coupled to the wire through a coupling capacitor.

摘要翻译： 本发明的一些实施例提供了用于高带宽片上通信的技术和系统。 在操作期间，系统接收将通过芯片中的导线传输的输入电压信号。 然后，该系统从输入电压信号产生一个或多个修改的电压信号。 接下来，系统通过相应的电容器驱动每个电压信号（即，输入电压信号和一个或多个修改的电压信号）。 然后，系统组合来自电容器的输出信号以获得组合电压信号。 接下来，系统通过电线传输组合的电压信号。 所传送的信号然后可以由滞后接收器接收，该滞后接收器通过耦合电容耦合到导线。

公开(公告)号：US20110248750A1

公开(公告)日：2011-10-13

申请号：US12758189

申请日：2010-04-12

申请人： Jae-sun Seo ,  Ronald Ho ,  Robert J. Drost ,  Robert D. Hopkins

发明人： Jae-sun Seo ,  Ronald Ho ,  Robert J. Drost ,  Robert D. Hopkins

IPC分类号： H03K3/00

CPC分类号： G06F13/4072 ,  G06F2213/0038 ,  H03K3/3565 ,  Y02D10/14 ,  Y02D10/151

摘要： Some embodiments of the present invention provide techniques and systems for high-bandwidth on-chip communication. During operation, the system receives an input voltage signal which is to be transmitted over a wire in a chip. The system then generates one or more modified voltage signals from the input voltage signal. Next, the system drives each of the voltage signals (i.e., the input voltage signal and the one or more modified voltage signals) through a respective capacitor. The system then combines the output signals from the capacitors to obtain a combined voltage signal. Next, the system transmits the combined voltage signal over the wire. The transmitted signals can then be received by a hysteresis receiver which is coupled to the wire through a coupling capacitor.

摘要翻译： 本发明的一些实施例提供了用于高带宽片上通信的技术和系统。 在操作期间，系统接收将通过芯片中的导线传输的输入电压信号。 然后，该系统从输入电压信号产生一个或多个修改的电压信号。 接下来，系统通过相应的电容器驱动每个电压信号（即，输入电压信号和一个或多个修改的电压信号）。 然后，系统组合来自电容器的输出信号以获得组合电压信号。 接下来，系统通过电线传输组合的电压信号。 所传送的信号然后可以由滞后接收器接收，该滞后接收器通过耦合电容耦合到导线。

公开(公告)号：US20240232718A9

公开(公告)日：2024-07-11

申请号：US18494330

申请日：2023-10-25

申请人： Jae-sun Seo ,  Jian Meng ,  Li Yang ,  Deliang Fan

发明人： Jae-sun Seo ,  Jian Meng ,  Li Yang ,  Deliang Fan

IPC分类号： G06N20/00

CPC分类号： G06N20/00

摘要： A method of training a machine learning algorithm comprises providing a set of input data, performing transforms on the input data to generate augmented data, to provide transformed base paths into machine learning algorithm encoders, segmenting the augmented data, calculating main base path outputs by applying a weighting to the segmented augmented data, calculating pruning masks from the input and augmented data to apply to the base paths of the machine learning algorithm encoders, the pruning masks having a binary value for each segment in the segmented augmented data, calculating sparse conditional path outputs by performing a computation on the segments of the segmented augmented data, and calculating a final output as a sum of the main base path outputs and the sparse conditional path outputs. A computer-implemented system for learning sparse features of a dataset is also disclosed.

公开(公告)号：US20240095528A1

公开(公告)日：2024-03-21

申请号：US18463778

申请日：2023-09-08

申请人： Jae-sun Seo ,  Jian Meng ,  Li Yang ,  Deliang Fan

发明人： Jae-sun Seo ,  Jian Meng ,  Li Yang ,  Deliang Fan

IPC分类号： G06N3/08 ,  G06N3/0495

CPC分类号： G06N3/08 ,  G06N3/0495

摘要： A method for increasing the temperature-resiliency of a neural network, the method comprising loading a neural network model into a resistive nonvolatile in-memory-computing chip, training the deep neural network model using a progressive knowledge distillation algorithm as a function of a teacher model, the algorithm comprising injecting, using a clean model as the teacher model, low-temperature noise values into a student model and changing, now using the student model as the teacher model, the low-temperature noises to high-temperature noises, and training the deep neural network model using a batch normalization adaptation algorithm, wherein the batch normalization adaptation algorithm includes training a plurality of batch normalization parameters with respect to a plurality of thermal variations.