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11.发明授权Method and apparatus for duplicating tag systems to maintain addresses of CPU data stored in write buffers external to a cache 失效用于复制标签系统以维持存储在高速缓存外部的写入缓冲器中的CPU数据的地址的方法和装置
公开(公告)号：US5978886A
公开(公告)日：1999-11-02
申请号：US785371
申请日：1997-01-17
申请人： Julie W. Moncton , Kenneth K. Chan
发明人： Julie W. Moncton , Kenneth K. Chan
CPC分类号： G06F12/0831
摘要： An apparatus and method for duplicating tag addresses to maintain addresses of central processing unit (CPU) data stored in write buffers external to a cache are disclosed. Advance notification of write transactions is issued to allow a subsystem that maintains duplicate cache tags to know in advance which write transactions are present in the CPU's buffers. Such information is used to keep duplicate tags for both the cache and any buffers that contain writes that are to be removed from the cache. The cache is preferably a direct mapped cache and the CPU preferably resides within a multiprocessor architecture. In the preferred embodiment, all write transactions are indirectly caused by a read transaction that is about to bring a line into the cache. Thus, a read transaction is issued by the CPU before the write transaction is issued. A field is added to the read transaction that indicates whether or not the read transaction has a corresponding line that must be written out of the cache and into a buffer, such that the duplicate tags duplicate both the CPU cache and the CPU write buffers.
摘要翻译： 公开了一种用于复制标签地址以维持存储在高速缓存外部的写缓冲器中的中央处理单元（CPU）的数据的装置和方法。 发出写入事务的预先通知，以允许维护重复的缓存标签的子系统事先知道CPU缓冲区中存在哪些写入事务。 这些信息用于为缓存和包含要从缓存中删除的写入的任何缓冲区保留重复的标签。 高速缓存优选地是直接映射高速缓存，并且CPU优选驻留在多处理器架构内。 在优选实施例中，所有写入事务间接地由即将将高速缓存行引入的读取事务引起。 因此，在发出写入事务之前，由CPU发出读取事务。 读取事务中添加一个字段，该事务指示读取事务是否具有必须从高速缓存写入缓冲区的相应行，使得重复的标记同时复制CPU高速缓存和CPU写入缓冲区。
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12.发明授权Wait state mechanism for a high speed bus which allows the bus to continue running a preset number of cycles after a bus wait is requested 失效一个高速总线的等待状态机制，允许总线在请求总线等待后继续运行预设的循环次数
公开(公告)号：US5339440A
公开(公告)日：1994-08-16
申请号：US933434
申请日：1992-08-21
CPC分类号： G06F13/4217
摘要： The present invention provides a protocol method for waiting the bus in a digital computer and an apparatus for implementing that protocol. By allowing the bus to continue running after a wait command has been asserted, modules on the computer bus are not required to respond instantly to the wait command. Information on the bus during the multiple cycles of the wait period is defined as invalid and valid data is driven on the bus after the wait period has expired. Bus driver modules are provided with a replay queue to replay, on the bus, data the driver module drove on the bus during the wait period if required.
摘要翻译： 本发明提供了一种在数字计算机中等待总线的协议方法和用于实现该协议的装置。 通过允许总线在等待命令被断言之后继续运行，计算机总线上的模块不需要立即响应等待命令。 在等待期间的多个周期内，总线上的信息被定义为无效，等待期结束后在总线上驱动有效的数据。 总线驱动器模块具有重播队列，用于在总线上播放驱动程序模块在等待期间在总线上驱动的数据（如果需要）。
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13.发明授权Method and system for verification of soft error handling with application to CMT processors 有权用于CMT处理器的软错误处理验证方法和系统公开(公告)号：US07320114B1
公开(公告)日：2008-01-15
申请号：US11049990
申请日：2005-02-02
CPC分类号： G06F11/263 , G06F11/261
摘要： A method provides for verifying soft error handling in an integrated circuit (IC) design. A diagnostic program is executed on a virtual IC based on the IC design using a simulator. A soft error is injected into the virtual IC to trigger hardware error correction in the virtual IC and a software exception. A record of a type and a location of the soft error at the time of the injecting is created. The error log generated by hardware error correction is then compared with the record of injected error, the hardware error correction being part of the virtual IC. An IC design flaw is indicated when a discrepancy exists between the error log and the record of the injected error.
摘要翻译： 一种用于验证集成电路（IC）设计中的软错误处理的方法。 基于使用模拟器的IC设计，在虚拟IC上执行诊断程序。 虚拟IC中注入软错误以触发虚拟IC中的硬件错误纠正和软件异常。 创建注射时软错误的类型和位置的记录。 然后将由硬件错误校正产生的错误日志与注入错误的记录进行比较，硬件错误校正是虚拟IC的一部分。 当错误日志和注入错误的记录之间存在差异时，会指示IC设计缺陷。
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14.发明授权Lipid-modified insulin incorporated liposomes for selectively delivering cytotoxic agents to hepatoma cells 有权脂质修饰的胰岛素引入的脂质体用于向肝癌细胞选择性递送细胞毒性剂
公开(公告)号：US06159931A
公开(公告)日：2000-12-12
申请号：US162869
申请日：1998-09-29
申请人： Kenneth K. Chan , Hong Mei
发明人： Kenneth K. Chan , Hong Mei
摘要： The present invention provides a lipid-modified insulin comprising an insulin molecule linked to an alkyl group by an amine linkage. Preferably, the alkyl group is a straight chain carbon comprising from about 14 to 20 carbon atoms. Preferably, the alkyl group is linked to the B1 phenylalanine or the B29 lysine. The present invention also provides a liposome comprising such lipid-modified insulin. Preferably, the liposomes are small unilamellar vesicles (SUVs) which have a particle size of less than 100 nm.The present invention also provides a method for making a lipid-modified insulin. The method comprises reacting the protein with a hydrophobic aldehyde in the presence a reducing agent to provide a lipid-modified insulin in which an amino acid of the insulin is linked to an alkyl group by an amine linkage.The present invention also relates to a method of killing hepatoma cells, particularly the hepatoma cells that are found in a hepatocellular carcinoma. The method comprises the steps of: providing liposomes containing a cytotoxic agent and having a lipid-modified insulin associated with the lipid bilayer thereof and exposing the hepatoma cells to the liposomes.
摘要翻译： 本发明提供了脂质修饰的胰岛素，其包含通过胺键与烷基连接的胰岛素分子。 优选地，烷基是包含约14至20个碳原子的直链碳。 优选地，烷基与B1苯丙氨酸或B29赖氨酸连接。 本发明还提供了包含这种脂质修饰的胰岛素的脂质体。 优选地，脂质体是粒径小于100nm的小单层囊泡（SUV）。 本发明还提供了制备脂质修饰的胰岛素的方法。 该方法包括使蛋白质与疏水性醛在还原剂存在下反应以提供脂质修饰的胰岛素，其中胰岛素的氨基酸通过胺键与烷基连接。 本发明还涉及一种杀死肝癌细胞的方法，特别是在肝细胞癌中发现的肝癌细胞。 该方法包括以下步骤：提供含有细胞毒性剂的脂质体并具有与其脂质双层相关的脂质修饰的胰岛素，并将肝癌细胞暴露于脂质体。
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15.发明授权
公开(公告)号：US5468499A
公开(公告)日：1995-11-21
申请号：US152493
申请日：1993-11-15
CPC分类号： A61K31/664 , A61K9/1271 , Y10S514/883
摘要： The present invention provides an anti cancer treatment which has an improved stability and does not produce acrolein. The invention includes dichlorodiethyl phosphoramide drugs including, for example, the cyclohexylamine salt phosphoramide mustard and isophosphoramide mustard and mixtures thereof, which have been entrapped by liposomes. Preferably the liposomes contain sphingomyelin and cholesterol.
摘要翻译： 本发明提供了具有改善的稳定性并且不产生丙烯醛的抗癌治疗。 本发明包括二氯二乙基磷酰胺药物，包括例如环己胺盐磷酰胺芥酸和异磷酰胺芥末及其混合物，其被脂质体包裹。 脂质体优选含有鞘磷脂和胆固醇。
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公开(公告)号：US07943568B2
公开(公告)日：2011-05-17
申请号：US12088846
申请日：2005-09-30
申请人： Kenneth K. Chan , Jin Xiao
发明人： Kenneth K. Chan , Jin Xiao
摘要： Compounds and methods useful for the treatment of cancer in subjects in need of such treatment. The compounds are metabolites of the compound FK228 which have been identified as possessing HDAC inhibitory activity and anticancer properties. Further provided are compounds and methods for inducing apoptosis in cancer cells. Further provided are compounds and methods for inhibiting HDAC in cancer cells.
摘要翻译： 可用于治疗需要这种治疗的受试者中的癌症的化合物和方法。 这些化合物是化合物FK228的代谢物，其被鉴定为具有HDAC抑制活性和抗癌特性。 还提供了诱导癌细胞凋亡的化合物和方法。 还提供了用于抑制癌细胞中HDAC的化合物和方法。
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公开(公告)号：US5524216A
公开(公告)日：1996-06-04
申请号：US242748
申请日：1994-05-13
IPC分类号： G06F12/08 , G06F12/10 , G06F13/36 , G06F13/40 , G06F15/173
CPC分类号： G06F13/4027
摘要： A computer system has a multi-tiered bus system. The multi-tiered bus system includes one or more local buses and a central bus connected to each local bus by a bus interface. In order to maintain one global view of transaction ordering, the processors on each local bus record bus transactions in an order on which the bus transactions appear on the central bus. To do this, bus transactions which are initiated on any local bus are forwarded to the central bus by the corresponding bus interface. The processors connected to the local bus do not record bus transactions when they are initiated on the local bus. Every transaction which occurs on the central bus is echoed back to every local bus by the corresponding bus interface. Each processor records bus transactions at the time they are echoed back to the local bus.
摘要翻译： 计算机系统具有多层总线系统。 多层总线系统包括一个或多个局部总线和通过总线接口连接到每个局部总线的中央总线。 为了保持交易排序的一个全局视图，每个本地总线上的处理器按照总线事务在中央总线上出现的顺序记录总线事务。 为此，在任何本地总线上启动的总线事务通过相应的总线接口转发到中央总线。 连接到本地总线的处理器在本地总线上启动时不会记录总线事务。 在中央总线上发生的每个事务通过相应的总线接口回传到每个局部总线。 每个处理器在回传到本地总线时记录总线事务。
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公开(公告)号：US4823338A
公开(公告)日：1989-04-18
申请号：US81081
申请日：1987-08-03
CPC分类号： H04L41/26 , H04L12/28 , H04L12/4641 , Y10S370/908
摘要： A system is disclosed for completing communication connections from end-users served by a connectionless (broadcast) type system in a manner which allows expansion of the calling area beyond the immediate physical limitations of the broadcast media. The system is based upon a device for mediating between the connectionless system and a connection oriented system. The device creates logical local area networks interconnectable by the connection oriented system. Calling user identification is used in conjunction with call completion data stored in a central memory for controlling all interconnections.
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公开(公告)号：US4821170A
公开(公告)日：1989-04-11
申请号：US40513
申请日：1987-04-17
申请人： David L. Bernick , Kenneth K. Chan , Wing M. Chan , Yie-Fong Dan , Duc M. Hoang , Zubair Hussain , Geoffrey I. Iswandhi , James E. Korpi , Martin W. Sanner , Jay A. Zwagerman , Steven G. Silverman , James E. Smith
发明人： David L. Bernick , Kenneth K. Chan , Wing M. Chan , Yie-Fong Dan , Duc M. Hoang , Zubair Hussain , Geoffrey I. Iswandhi , James E. Korpi , Martin W. Sanner , Jay A. Zwagerman , Steven G. Silverman , James E. Smith
IPC分类号： G06F11/18 , G06F9/52 , G06F11/00 , G06F11/10 , G06F13/12 , G06F13/28 , G06F13/40 , G06F15/16
CPC分类号： G06F13/28 , G06F13/122 , G06F13/4022 , G06F11/10
摘要： In a digital computer system which employs a plurality of host processors, at least two system buses and a plurality of peripheral input/output ports, an input/output system is provided whereby ownership of the input/output channels is shared. The device controller employs a first port controller having a first ownership latch, a second port controller having a second ownership latch, a first bus, a dedicated microprocessor having control over the first bus (the MPU bus), a second, higher-speed bus, a multiple-channel direct memory access (DMA) controller which is a state machine which controls the second bus (the data buffer bus), a bus switch for exchanging data between buses, a multiple device peripheral device interface, namely a Small Computer System Interface (SCSI), and at least provision for interface with data communication equipment (DCEs) or data terminal equipment (DTEs). The DMA controller arbitrates data bus usage and can allocate alternate bus clock cycles in response to requests to exchange data and is capable of supporting overlapping transfers. The microprocessor is allowed access to the data buffer bus only if the data buffer bus is not in use for data transfer. The latches associated with each port grant ownership to either port or both ports allowing data exchange between addressed peripheral devices and requesting ports.
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