公开(公告)号：US20070059833A1

公开(公告)日：2007-03-15

申请号：US11470906

申请日：2006-09-07

Applicant: Linhong Li ,  Linda Liu ,  Cornell Allen ,  Rama Shivakumar ,  James Brady

Inventor： Linhong Li ,  Linda Liu ,  Cornell Allen ,  Rama Shivakumar ,  James Brady

IPC: C12N15/87

CPC classification number: C12N15/87 ,  C12N9/22 ,  C12N2501/70

Abstract: The present invention concerns methods and compositions for improving viability and transgene expression in transfected cells. In one embodiment, the present invention provides a method for increasing the viability of a transfected cell, the method comprising: transfecting a cell with a nucleic acid sequence; and contacting the transfected cell with a nuclease in a manner effective to enhance the viability of the transfected cell.

Abstract translation: 本发明涉及用于改善转染细胞中活力和转基因表达的方法和组合物。 在一个实施方案中，本发明提供了用于增加转染细胞的存活力的方法，所述方法包括：用核酸序列转染细胞; 并以有效增强转染细胞活力的方式使转染的细胞与核酸酶接触。

公开(公告)号：US20050239041A1

公开(公告)日：2005-10-27

申请号：US11105140

申请日：2005-04-13

Applicant: James Brady ,  James Winchester ,  Vadim Davankov ,  Maria Tsyurupa ,  Ludmila Pavlova ,  Frank Norris ,  Peter Quartararo ,  Jamie Salsberg

Inventor： James Brady ,  James Winchester ,  Vadim Davankov ,  Maria Tsyurupa ,  Ludmila Pavlova ,  Frank Norris ,  Peter Quartararo ,  Jamie Salsberg

IPC: A01N1/02 ,  A61B20060101 ,  A61M1/14 ,  A61M1/16 ,  A61M1/28 ,  A61M1/34 ,  A61M1/36 ,  B01D15/00 ,  B01D15/04 ,  B01D39/04 ,  B01D61/00 ,  B01D61/24 ,  B01J20/26 ,  B01J20/32

CPC classification number: A61M1/3679 ,  A01N1/02 ,  A01N1/0226 ,  A61M1/16 ,  A61M1/1678 ,  A61M1/1686 ,  A61M1/169 ,  A61M1/1696 ,  A61M1/1698 ,  A61M1/28 ,  A61M1/281 ,  A61M1/284 ,  A61M1/34 ,  A61M1/3403 ,  A61M1/3486 ,  A61M1/3681 ,  B01D39/04 ,  B01J20/26 ,  B01J20/261 ,  B01J20/321 ,  B01J20/327 ,  B01J20/3272 ,  B01J20/3293

Abstract: Devices, systems, and methods reduce levels of pro-inflammatory or anti-inflammatory stimulators or mediators in blood by selective adsorption. The devices, systems, and methods are useful in situations where abnormal levels of or unregulated or excessive interaction among pro-inflammatory or anti-inflammatory stimulators or mediators occur, or during events that do induce or have the potential for inducing abnormal production of pro-inflammatory or anti-inflammatory stimulators or mediators. The devices, systems, and methods serve to prevent, control, reduce, or alleviate the severity of the inflammatory response and disease states that are associated with abnormal levels of or unregulated or excessive interaction among pro-inflammatory or anti-inflammatory stimulators or mediators.

Abstract translation: 装置，系统和方法通过选择性吸附降低血液中促炎症或抗炎刺激物或介质的水平。 器官，系统和方法适用于在促炎症或抗炎刺激物或介质发生异常水平或不协调或过度相互作用的情况下，或在诱导或有可能引起异常生产促炎症 炎性或抗炎刺激物或介质。 装置，系统和方法用于预防，控制，减少或减轻与促炎症或抗炎刺激剂或介体的异常水平或不协调或过度相互作用相关的炎症反应和疾病状态的严重性。

公开(公告)号：US06157578A

公开(公告)日：2000-12-05

申请号：US354398

申请日：1999-07-15

Applicant: James Brady

Inventor： James Brady

IPC: G11C11/401 ,  G11C7/06 ,  G11C7/10 ,  G11C7/22 ,  G11C11/409 ,  G11C7/00

CPC classification number: G11C7/1006 ,  G11C7/065 ,  G11C7/22 ,  G11C2207/2281 ,  G11C2207/229

Abstract: A device and method for accessing a row of data in a semiconductor memory device in a single operation is disclosed. The device includes a row of latches having a width which matches the width of the memory array in the semiconductor memory device. The device includes precharge and equilibration circuitry associated with the row of latches and the row of sense amplifiers in device, and timing circuitry for controlling the operation of each in performing full page read and write operations. Writing a full row of data from the row of latches into a selected row of memory cells includes the steps of disconnecting the row of sense amplifiers from the reference voltage sources; equalizing voltage levels appearing on the bit lines of the semiconductor memory and the sense amplifiers; connecting a row of memory cells to the bit lines; driving at least one bit line of each pair of bit lines to a voltage level representing the data value stored in the corresponding latch; coupling the sense amplifiers to the reference voltage sources for powering the sense amplifiers; and disconnecting the row of memory cells from the bit lines.

Abstract translation: 公开了一种用于在单个操作中访问半导体存储器件中的数据行的装置和方法。 该器件包括具有与半导体存储器件中的存储器阵列的宽度匹配的宽度的一排锁存器。 该装置包括与锁存器行和器件中的读出放大器行相关联的预充电和平衡电路，以及用于在执行全页读和写操作时控制每个操作的定时电路。 将锁存器行的全行数据写入选定行的存储单元包括以下步骤：将读出放大器行与参考电压源断开; 均衡出现在半导体存储器和读出放大器的位线上的电压电平; 将一行存储单元连接到位线; 将每对位线的至少一个位线驱动到表示存储在相应锁存器中的数据值的电压电平; 将读出放大器耦合到参考电压源以为读出放大器供电; 并将该行的存储单元从位线断开。

公开(公告)号：US06111801A

公开(公告)日：2000-08-29

申请号：US302598

申请日：1999-04-30

Applicant: James Brady

Inventor： James Brady

IPC: G01R31/28 ,  G01R31/3185 ,  G06F12/16 ,  G11C11/401 ,  G11C11/413 ,  G11C17/00 ,  G11C29/02 ,  G11C29/12 ,  G11C29/00

CPC classification number: G11C29/02

Abstract: A technique for testing wordline and related circuitry of a memory array is disclosed. The memory array includes a plurality of memory cells arranged in a plurality of rows, wherein each of the plurality of rows has a respective wordline connected to respective ones of the plurality of memory cells. The related circuitry includes a decode circuit connected to each of the respective wordlines for activating at least one of the respective wordlines based upon a corresponding address signal that is decoded by the decode circuit. The technique involves applying an address signal to the decode circuit so as to activate a corresponding one of the respective wordlines, and then monitoring the corresponding one of the respective wordlines so as to determine if the corresponding one of the respective wordlines has been activated and thereby determine if the memory array and related circuitry are operating in a proper manner.

Abstract translation: 公开了一种用于测试存储器阵列的字线和相关电路的技术。 存储器阵列包括以多行布置的多个存储单元，其中多行中的每一行具有连接到多个存储单元中的相应存储单元的相应字线。 相关电路包括连接到每个相应字线的解码电路，用于基于由解码电路解码的相应地址信号激活相应字线中的至少一个。 该技术涉及将一个地址信号应用于解码电路，以激活相应的字线中相应的一个，然后监视相应的字线中相应的一个，以便确定相应的字线中相应的一个是否已被激活 确定存储器阵列和相关电路是否以适当的方式工作。

公开(公告)号：US6107865A

公开(公告)日：2000-08-22

申请号：US429964

申请日：1999-10-29

Applicant: James Brady

Inventor： James Brady

IPC: H01L21/761 ,  H01L27/092 ,  H03F1/30 ,  H03F3/01

CPC classification number: H01L27/092 ,  H01L21/761 ,  H03F1/305

Abstract: A battery backed-up semiconductor device employs a Vss switching configuration to provide uninterrupted battery power to critical circuitry of the device even in the event of external conditions, such as undershoot, that threaten to corrupt data stored by the device. Both primary power and battery power, when needed, are supplied to floating wells of the device rather than to the device substrate, making the device immune to undershoots that can short the battery to the device substrate and corrupt data stored by the device. The device substrate is permanently tied to the positive power supply voltage and the positive terminal of the battery voltage and is therefore not subject to the concerns associated with switching from a failed primary power supply to the back-up battery power supply.

Abstract translation: 电池备份的半导体器件采用Vss切换配置，即使在外部条件（例如下冲）的情况下，也可能对设备的关键电路提供不间断的电池电力，这可能会损坏设备存储的数据。 当需要时，主电源和电池电源都被提供给设备的浮动阱而不是设备基板，从而使设备免受可能使电池与设备基板短路并损坏设备存储的数据的下冲。 设备基板永久地连接到正电源电压和电池电压的正极端子，因此不会受到从故障主电源切换到备用电池电源的关注。

公开(公告)号：US6067263A

公开(公告)日：2000-05-23

申请号：US287803

申请日：1999-04-07

Applicant: James Brady

Inventor： James Brady

IPC: G01R31/28 ,  G11C11/401 ,  G11C29/02 ,  G11C29/12 ,  G11C29/50 ,  G11C7/00 ,  G11C7/02

CPC classification number: G11C29/02

Abstract: A dynamic random access memory (DRAM) circuit is provided that utilizes a testing system and method to determine the sensitivity of a sense amplifier. More specifically, the DRAM circuit, in determining the sensitivity of the sense amplifier, utilizes a testing system to independently control the magnitude of a voltage differential appearing between a pair of bit lines and sensed by the sense amplifier. The sensitivity of the sense amplifier is then able to be determined by monitoring an input/output signal in response to sensing the known voltage differential. The testing system controls the magnitude of the voltage differential appearing between the bit lines by enabling a first dummy cell to transfer a first reference charge onto a first bit line and by enabling a second dummy cell to transfer a second reference charge onto a second bit line.

Abstract translation: 提供了一种动态随机存取存储器（DRAM）电路，其利用测试系统和方法来确定读出放大器的灵敏度。 更具体地说，DRAM电路在确定读出放大器的灵敏度时利用测试系统来独立地控制出现在一对位线之间并由感测放大器感测的电压差的幅度。 然后能够通过响应于感测已知电压差来监视输入/输出信号来确定读出放大器的灵敏度。 测试系统通过使第一虚拟单元能够将第一参考电荷传送到第一位线上并且通过使第二虚拟单元将第二参考电荷转移到第二位线上来控制出现在位线之间的电压差的大小 。

公开(公告)号：US5713479A

公开(公告)日：1998-02-03

申请号：US719455

申请日：1996-09-25

Applicant: James Brady

Inventor： James Brady

IPC: B65D41/04

CPC classification number: B65D41/0471

Abstract: An anti-backoff screw cap construction for a container neck having a thread with a downwardly-facing pressure face and an upwardly-facing relief face. The cap has a depending skirt having an internal thread with an upwardly-facing pressure face for engagement with the downwardly-facing pressure face of the container neck thread. Engagement results in tightening of the cap on the container neck when the cap is turned in a screwing-on direction. The cap thread has a downwardly-facing relief face having as an anti-backoff structure, an elongate, substantially helical, resilient projecting bead which is integral with the cap thread, the bead being coextensive with an uppermost portion of its downwardly-facing relief face and being directly engageable by the upwardly-facing relief face of the container neck thread. The projecting bead is resiliently deformed by its engagement with the upwardly-facing relief face of the container neck thread when the cap is turned in its screwing-on direction. The deformed projecting bead elastically and frictionally grips the upwardly-facing relief face of the container neck thread so as to reduce the tendency for the cap to become inadvertently unscrewed from its fully screwed-on position. A highly effective retention of the cap results, without the need for complex molded locking lugs, teeth or the like.

Abstract translation: 一种用于容器颈部的防回退螺旋盖构造，其具有具有面向下的压力面和面向上的浮雕面的螺纹。 帽具有一个具有内螺纹的悬垂裙部，该内螺纹具有面向上的压力面，用于与容器颈线的面向下的压力面接合。 当盖子沿螺旋方向转动时，接合会导致收紧容器颈部的盖子。 盖螺纹具有向下的浮雕面，其具有作为防回退结构的细长的，基本上螺旋的弹性突出的凸缘，其与盖螺纹成一体，所述凸缘与其向下的浮雕面的最上部共同延伸 并且可以通过容器颈部线的向上的浮雕面直接接合。 当盖沿其拧紧方向转动时，突出的凸缘通过其与容器颈线的向上的浮雕面的接合而弹性变形。 变形的突起珠弹性地并且摩擦地夹住容器颈线的向上的浮雕面，以便减小帽被无意地从其完全拧紧的位置拧开的倾向。 高效地保持盖的结果，而不需要复杂的模制锁定凸耳，牙齿等。

公开(公告)号：US5311467A

公开(公告)日：1994-05-10

申请号：US864481

申请日：1992-04-07

Applicant: Mark A. Lysinger ,  William C. Slemmer ,  James Brady ,  David C. McClure

Inventor： Mark A. Lysinger ,  William C. Slemmer ,  James Brady ,  David C. McClure

IPC: G11C11/41 ,  G11C8/08 ,  G11C11/407 ,  G11B7/00

CPC classification number: G11C8/08

Abstract: A memory is disclosed having a plurality of memory cells in a memory array arranged in rows and columns, each of the memory cells capable of storing a logic state therein. Each pair of bit lines is associated with one of the columns. A column decoder selects a column in the array responsive to a column address. A plurality of word line drivers selects, in response to a row address, a row of memory cells for connection with their associated pair of bit lines. A plurality of row isolation circuits isolates and enables a selected group of memory cells of each row from the remainder of the row in response to a bulk write signal. Each row isolation circuit has a conduction path between its associated word line driver and the selected memory cells in the associated row. A bulk write signal is sent to each column containing the selected memory cells. A first logic state is then written into the selected memory cells in response to the bulk write signal.

Abstract translation: 公开了一种存储器，其具有以行和列排列的存储器阵列中的多个存储器单元，每个存储器单元能够存储其中的逻辑状态。 每对位线与其中一列相关联。 列解码器响应于列地址选择数组中的列。 多个字线驱动器响应于行地址选择用于与其相关联的位线对连接的一行存储器单元。 多个行隔离电路响应于批量写入信号而隔离并使能来自行的其余部分的每行的选定组的存储单元。 每行隔离电路在其相关联的字线驱动器和相关联的行中的所选择的存储器单元之间具有传导路径。 批量写信号被发送到包含所选存储单元的每列。 然后响应于批量写入信号将第一逻辑状态写入所选择的存储器单元。

公开(公告)号：US5151387A

公开(公告)日：1992-09-29

申请号：US516272

申请日：1990-04-30

Applicant: James Brady ,  Tsiu C. Chan ,  David S. Culver

Inventor： James Brady ,  Tsiu C. Chan ,  David S. Culver

IPC: H01L23/52 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L23/53271 ,  H01L23/5226 ,  H01L2924/0002 ,  Y10S148/019 ,  Y10T428/24917 ,  Y10T428/24926

Abstract: A contact structure provides electrical contact between two polycrystalline silicon interconnect layers. The lower layer has a silicide layer on its upper surface. The upper polycrystalline silicon layer can be doped with a different conductivity type, and makes an ohmic contact with the silicided region of the lower polycrystalline silicon layer.

公开(公告)号：US20110295689A1

公开(公告)日：2011-12-01

申请号：US13115155

申请日：2011-05-25

Applicant: James Brady

Inventor： James Brady

IPC: G06Q30/00 ,  G06F17/30 ,  G06F15/16

CPC classification number: G06Q30/0256 ,  G06Q30/0241 ,  G06Q30/0269

Abstract: A method for presenting tailored content to a user, comprising: presenting a central coordinating interface to a client; Generating a portion of client specific computer code, including a unique site identification token for a client site and at least one operating parameter; Integrating the client specific computer code into the client site, serving at least one user the client site having integrated client specific computer code therein and giving the option to download an end-user application; Sending a request with at least one request parameter when a user selects to download the end-user application; Processing the request parameters and the operating parameters to dynamically generate an end-user application; providing the end-user application to the user, which presents tailored content to the user according to at least one of detail, request parameter and operating parameter.

Abstract translation: 一种用于向用户呈现定制内容的方法，包括：向客户端呈现中央协调界面; 生成客户端特定计算机代码的一部分，包括客户端站点的唯一站点标识令牌和至少一个操作参数; 将客户端特定的计算机代码集成到客户端站点中，为至少一个用户提供具有在其中集成了客户端特定计算机代码的客户端站点，并给出下载最终用户应用程序的选项; 当用户选择下载最终用户应用时，发送具有至少一个请求参数的请求; 处理请求参数和操作参数以动态生成最终用户应用程序; 向用户提供最终用户应用程序，其根据细节，请求参数和操作参数中的至少一个向用户呈现量身定制的内容。