公开(公告)号：US07074657B2

公开(公告)日：2006-07-11

申请号：US10706948

申请日：2003-11-14

申请人： James N. Pan ,  John G. Pellerin ,  Jon Cheek

发明人： James N. Pan ,  John G. Pellerin ,  Jon Cheek

IPC分类号： H01L21/336

CPC分类号： H01L29/78696 ,  H01L29/78639

摘要： A multiple-channel semiconductor device has fully or partially depleted quantum wells and is especially useful in ultra large scale integration devices, such as CMOSFETs. Multiple channel regions are provided on a substrate with a gate electrode formed on the uppermost channel region, separated by a gate oxide, for example. The vertical stacking of multiple channels and the gate electrode permit increased drive current in a semiconductor device without increasing the silicon area occupied by the device.

摘要翻译： 多通道半导体器件具有完全或部分耗尽的量子阱，并且在超大规模集成器件（例如CMOSFET）中特别有用。 多个通道区域设置在基板上，其栅电极形成在最上通道区域上，例如由栅极氧化物分隔开。 多通道和栅电极的垂直堆叠允许增加半导体器件中的驱动电流，而不增加器件占用的硅面积。

公开(公告)号：US20060118918A1

公开(公告)日：2006-06-08

申请号：US11006747

申请日：2004-12-08

申请人： Andrew Waite ,  Jon Cheek

发明人： Andrew Waite ,  Jon Cheek

IPC分类号： H01L29/04 ,  H01L29/06 ,  H01L27/12

CPC分类号： H01L21/823807 ,  H01L21/76254 ,  H01L21/76267 ,  H01L21/76283 ,  H01L21/823412 ,  H01L21/823481 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/045

摘要： A semiconductor device comprising a substrate having a first crystal orientation is provided. A first insulating layer overlies the substrate and a plurality of silicon layers overlie the first insulating layer. A first silicon layer comprises silicon having a second crystal orientation and a crystal plane. A second silicon layer comprises silicon having the second crystal orientation and a crystal plane that is substantially orthogonal to the crystal plane of the first silicon layer. Because holes have higher mobility in the (110) plane than the (100) plane, while electrons have higher mobility in (100) plane than the (110) plane, semiconductor device performance can be enhanced by the selection of silicon layers with certain crystal plane orientations. In addition, a method of forming a semiconductor device is provided. A silicon-on-insulator structure comprising a first silicon substrate having a first crystal orientation with a first insulating layer formed thereon and a first silicon layer having a second crystal orientation and a crystal plane overlying the first insulating layer is bonded to a second silicon substrate. The second silicon substrate has the second crystal orientation and a crystal plane and a second insulating layer formed thereon. The second silicon substrate comprises a line of defects created by implanting hydrogen ion into the second silicon substrate. The crystal plane of the second silicon substrate is oriented substantially orthogonal to the crystal plane of the first silicon layer. The second silicon substrate is split and removed along the line of defects leaving behind the second insulating layer and a second silicon layer on the silicon-on-insulator structure. A plurality of devices with different crystal orientations can be subsequently formed on a single, planar silicon-on-insulator structure by selectively etching the silicon-on-insulator structure down to silicon layers of different crystal orientations, growing selective epitaxial silicon layers in the etched regions, and subsequently planarizing the silicon-on-insulator structure by chemical-mechanical polishing.

公开(公告)号：US06638829B1

公开(公告)日：2003-10-28

申请号：US09199960

申请日：1998-11-25

申请人： Jon Cheek ,  Derick Wristers ,  Mark I. Gardner

发明人： Jon Cheek ,  Derick Wristers ,  Mark I. Gardner

IPC分类号： H01L21336

CPC分类号： H01L29/66628 ,  H01L21/28079 ,  H01L29/66545

摘要： A semiconductor structure and a process for its manufacture. A metal gate electrode is formed on a semiconductor substrate, the gate electrode being between nitride spacers. Lightly-doped drain regions and source/drain regions are disposed in the substrate and aligned with the electrode and spacers. A silicide contact layer is disposed over an epitaxial layer on the substrate over the source/drain regions.

摘要翻译： 半导体结构及其制造方法。 金属栅电极形成在半导体衬底上，栅极位于氮化物衬垫之间。 轻掺杂漏极区和源/漏区设置在衬底中并与电极和间隔物对准。 硅化物接触层设置在源/漏区上的衬底上的外延层上。

公开(公告)号：US6159812A

公开(公告)日：2000-12-12

申请号：US20175

申请日：1998-02-06

申请人： Jon Cheek ,  William A. Whigham ,  Derick Wristers

发明人： Jon Cheek ,  William A. Whigham ,  Derick Wristers

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L21/8238

CPC分类号： H01L29/6659 ,  H01L21/26513 ,  H01L21/823814 ,  H01L29/6656

摘要： A method for slowing the diffusion of boron ions in a CMOS structure includes a preanneal step which can be incorporated as part of a step in which silane is deposited across the surface of the wafer. After the last implant on a CMOS device, silane (SiH.sub.4) is deposited over the surface of the wafer using a chemical vapor deposition (CVD) tool. The deposition of silane is done at 400.degree. C. The temperature is raised in the CVD tool to a temperature in the range of 550.degree. C. to 650.degree. C. and held for 30-60 minutes. This temperature does not affect the thin film of silicon which is formed from the silane, yet provides the necessary thermal cycle to "repair" the crucial first 200 .ANG. to 600 .ANG. of the silicon surface. Normal processing steps, including a rapid thermal anneal for 30 seconds at 1025.degree. C. follow. The RTA is necessary to activate the dopants (arsenic and boron) in the source and drain of the respective devices. The boron dopant species diffuses less during subsequent rapid thermal anneal cycles since the crucial first 200 .ANG. to 600 .ANG. of the silicon surface have been repaired using this preanneal step.

摘要翻译： 用于减缓CMOS结构中硼离子的扩散的方法包括预退火步骤，其可以作为其中硅烷沉积在晶片的表面上的步骤的一部分而被并入。 在CMOS装置上最后一次植入之后，使用化学气相沉积（CVD）工具将硅烷（SiH4）沉积在晶片的表面上。 硅烷的沉积在400℃下进行。将温度在CVD工具中升高至550℃至650℃的温度，并保持30-60分钟。 该温度并不影响由硅烷形成的硅薄膜，而是提供了必要的热循环，以“修复”硅表面的至关重要的第一个200 ANGSTROM至600 ANGSTROM。 正常加工步骤，包括在1025℃快速热退火30秒。 RTA需要激活各个器件的源极和漏极中的掺杂剂（砷和硼）。 在随后的快速热退火循环中硼掺杂物种类扩散较少，因为使用该预退火步骤修复了硅表面的至关重要的第一个200 ANGSTROM至600 ANGSTROM。

公开(公告)号：US6114211A

公开(公告)日：2000-09-05

申请号：US195336

申请日：1998-11-18

申请人： H. Jim Fulford ,  Jon Cheek ,  Derick J. Wristers ,  James Buller

发明人： H. Jim Fulford ,  Jon Cheek ,  Derick J. Wristers ,  James Buller

IPC分类号： H01L21/336 ,  H01L29/10

CPC分类号： H01L29/66492 ,  H01L29/1083 ,  H01L29/6653 ,  H01L29/6659

摘要： One method of forming a semiconductor device includes forming a gate electrode on a substrate and then forming a spacer adjacent to a sidewall of the gate electrode. An active region is formed in the substrate adjacent to the spacer and spaced apart from the gate electrode using a first dopant material of a first conductivity type. A protecting layer is formed over the active region and adjacent to the spacer. At least a portion of the spacer is then removed to form an opening between the protecting layer and the gate electrode. In some instances, the spacer may be formed by independent deposition of two different materials (e.g., silicon nitride and silicon dioxide), one of which can be selectively removed with respect to the other. A lightly-doped region is formed in the substrate adjacent to the gate electrode using a second dopant material of the first conductivity type. This lightly-doped region may be formed, for example, prior to formation of the spacer, between the formation of two portions of the spacer, or after removing at least a portion of the spacer. A halo region is formed through the opening resulting from removing a portion of the spacer. The halo region is deeper in the substrate than the lightly-doped region and is adjacent to the active region. The halo region is formed using a third dopant material of a conductivity type different than the first conductivity type.

摘要翻译： 形成半导体器件的一种方法包括在衬底上形成栅电极，然后形成与栅电极的侧壁相邻的间隔物。 使用第一导电类型的第一掺杂剂材料，在与衬垫相邻的衬底中形成有源区，并与栅电极间隔开。 保护层形成在有源区上并与隔片相邻。 然后去除间隔物的至少一部分以在保护层和栅电极之间形成开口。 在一些情况下，可以通过独立沉积两种不同材料（例如，氮化硅和二氧化硅）来形成隔离物，其中一种可以相对于另一种材料选择性地去除。 使用第一导电类型的第二掺杂剂材料在与栅电极相邻的衬底中形成轻掺杂区域。 该轻掺杂区域例如可以在形成间隔物之前，在间隔物的两个部分的形成之间或在移除间隔物的至少一部分之后形成。 通过从隔离物的一部分去除而形成的晕圈形成。 卤素区域在衬底中比轻掺杂区域更深，并且与有源区域相邻。 卤素区域是使用不同于第一导电类型的导电类型的第三掺杂剂材料形成的。

公开(公告)号：US6074906A

公开(公告)日：2000-06-13

申请号：US958534

申请日：1997-10-27

申请人： Jon Cheek ,  Derick J. Wristers ,  H. Jim Fulford

发明人： Jon Cheek ,  Derick J. Wristers ,  H. Jim Fulford

IPC分类号： H01L21/8238

CPC分类号： H01L21/823864

摘要： A CMOS semiconductor device having NMOS source/drain regions formed using multiple spacers has at least one NMOS region and at least one PMOS region. A first n-type dopant is selectively implanted into an NMOS active region of the substrate adjacent a NMOS gate electrode to form a first n-doped region in the NMOS active region. A first NMOS spacer is formed on a sidewall of the NMOS gate electrode and a first PMOS spacer on a sidewall of a PMOS gate electrode. A second n-type dopant is selectively implanted into the NMOS active region using the first NMOS spacer as a mask. A p-type dopant is selectively implanted into a PMOS active region using the first PMOS spacer as a mask to form a first p-doped region in the PMOS active region. A second NMOS spacer and a second PMOS spacer are formed adjacent the first NMOS spacer and first PMOS spacer, respectively. A third n-type dopant is selectively implanted into the NMOS active region using the second NMOS spacer as a mask to form a third n-doped region deeper than the second n-doped region in the NMOS active region. A second p-type dopant is selectively implanted into the PMOS active region using the second PMOS spacer as a mask to form a second p-doped region in the PMOS active region deeper than the first p-doped region.

摘要翻译： 具有使用多个间隔物形成的NMOS源极/漏极区域的CMOS半导体器件具有至少一个NMOS区域和至少一个PMOS区域。 第一n型掺杂剂被选择性地注入到与NMOS栅电极相邻的衬底的NMOS有源区中，以在NMOS有源区中形成第一n掺杂区。 第一NMOS间隔物形成在NMOS栅电极的侧壁和PMOS栅电极的侧壁上的第一PMOS间隔物上。 使用第一NMOS间隔物作为掩模，将第二n型掺杂剂选择性地注入NMOS有源区。 使用第一PMOS间隔物作为掩模将p型掺杂剂选择性地注入PMOS有源区，以在PMOS有源区中形成第一p掺杂区。 分别与第一NMOS间隔物和第一PMOS间隔物相邻地形成第二NMOS间隔物和第二PMOS间隔物。 使用第二NMOS间隔物作为掩模，将第三n型掺杂剂选择性地注入NMOS有源区，以形成比NMOS有源区中的第二n掺杂区更深的第三n掺杂区。 使用第二PMOS间隔物作为掩模将第二p型掺杂剂选择性地注入到PMOS有源区中，以在PMOS有源区中形成比第一p掺杂区更深的第二p掺杂区。

公开(公告)号：US5977600A

公开(公告)日：1999-11-02

申请号：US2695

申请日：1998-01-05

申请人： Derick Wristers ,  Jon Cheek ,  H. James Fulford

发明人： Derick Wristers ,  Jon Cheek ,  H. James Fulford

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/762 ,  H01L21/768 ,  H01L29/94

CPC分类号： H01L21/28211 ,  H01L21/28176 ,  H01L21/762 ,  H01L29/6656 ,  H01L29/6659 ,  H01L21/76895 ,  H01L23/485 ,  H01L2924/0002 ,  Y10S257/90

摘要： The formation of a shortage protection region is disclosed. In one embodiment, a method includes three steps. In the first step, a first ion implantation is applied to form lightly doped regions within a semiconductor substrate adjacent to sidewalls of a gate over the substrate. In the second step, two spaces are formed on the substrate, each adjacent to a sidewall of the gate, so that a second ion implantation forms heavily doped regions within the substrate adjacent to the first spacers. In the third step, two additional spacers are formed on the substrate, each overlapping and extending beyond a corresponding spacer previously formed. Thus, a third ion implantation forms lightly doped shortage protection regions within the substrate adjacent to the spacers most recently formed.

摘要翻译： 公开了形成短缺保护区域。 在一个实施例中，一种方法包括三个步骤。 在第一步骤中，施加第一离子注入以在与衬底上的栅极的侧壁相邻的半导体衬底内形成轻掺杂区域。 在第二步骤中，在衬底上形成两个相邻于栅极的侧壁的空间，使得第二离子注入在邻近第一间隔物的衬底内形成重掺杂区域。 在第三步骤中，在衬底上形成两个附加间隔物，每个间隔物重叠并延伸超过预先形成的相应间隔物。 因此，第三离子注入在与最近形成的间隔物相邻的衬底内形成轻掺杂的短缺保护区。

公开(公告)号：US5970311A

公开(公告)日：1999-10-19

申请号：US961980

申请日：1997-10-31

申请人： Jon Cheek ,  Daniel Kadosh ,  Derick J. Wristers

发明人： Jon Cheek ,  Daniel Kadosh ,  Derick J. Wristers

IPC分类号： H01L21/66 ,  H01L23/544 ,  H01L21/00 ,  G01R31/26

CPC分类号： H01L22/20 ,  H01L22/34 ,  H01L2924/0002

摘要： A method and structure for optimizing the performance of a semiconductor device having dense transistors. A method consistent with the present invention includes forming a first test structure on a first substrate portion. The first test structure includes a transistor having a gate electrode formed at a design width and at a first line spacing similar to the line spacing of a dense transistor. One or more electrical properties the transistor of the first test structure is measured. A second test structure is formed on a second substrate portion. The second test structure includes a transistor having a gate electrode formed at the same design width as the transistor of the first test structure and at a second line spacing greater than the first line spacing. One or more electrical properties of the transistor of the second test structure are measured. Using the measured one or more electrical properties, one or more relationships are developed between the measured one or more electrical properties and the transistors at the first line spacing and the second line spacing.

摘要翻译： 一种用于优化具有致密晶体管的半导体器件的性能的方法和结构。 与本发明一致的方法包括在第一衬底部分上形成第一测试结构。 第一测试结构包括晶体管，其晶体管具有以类似于致密晶体管的线间距的设计宽度和第一行间距形成的栅电极。 测量第一测试结构的晶体管的一个或多个电特性。 在第二基板部分上形成第二测试结构。 第二测试结构包括晶体管，其晶体管具有与第一测试结构的晶体管相同的设计宽度并且在大于第一线间距的第二线间距处形成栅电极。 测量第二测试结构的晶体管的一个或多个电特性。 使用所测量的一个或多个电性能，在所测量的一个或多个电性能和在第一线间距和第二线间距处的晶体管之间形成一个或多个关系。

公开(公告)号：US07253484B2

公开(公告)日：2007-08-07

申请号：US11445345

申请日：2006-06-02

申请人： James N. Pan ,  John G. Pellerin ,  Jon Cheek

发明人： James N. Pan ,  John G. Pellerin ,  Jon Cheek

IPC分类号： H01L27/088 ,  H01L29/78 ,  H01L21/336

CPC分类号： H01L29/78696 ,  H01L29/78639

摘要： A multiple-channel semiconductor device has fully or partially depleted quantum wells and is especially useful in ultra large scale integration devices, such as CMOSFETs. Multiple channel regions are provided on a substrate with a gate electrode formed on the uppermost channel region, separated by a gate oxide, for example. The vertical stacking of multiple channels and the gate electrode permit increased drive current in a semiconductor device without increasing the silicon area occupied by the device.

摘要翻译： 多通道半导体器件具有完全或部分耗尽的量子阱，并且在超大规模集成器件（例如CMOSFET）中特别有用。 多个通道区域设置在基板上，其栅电极形成在最上通道区域上，例如由栅极氧化物分隔开。 多通道和栅电极的垂直堆叠允许增加半导体器件中的驱动电流，而不增加器件占用的硅面积。

公开(公告)号：US20050196928A1

公开(公告)日：2005-09-08

申请号：US10791759

申请日：2004-03-04

申请人： Douglas Bonser ,  Johannes Groschopf ,  Srikanteswara Dakshina-Murthy ,  John Pellerin ,  Jon Cheek

发明人： Douglas Bonser ,  Johannes Groschopf ,  Srikanteswara Dakshina-Murthy ,  John Pellerin ,  Jon Cheek

IPC分类号： H01L21/3105 ,  H01L21/762 ,  H01L21/336

CPC分类号： H01L21/76224

摘要： STI divot formation is eliminated or substantially reduced by employing a very thin nitride polish stop layer, e.g., no thicker than 400 Å. The very thin nitride polish stop layer is retained in place during subsequent masking, implanting and cleaning steps to form dopant regions, and is removed prior to gate oxide and gate electrode formation.

摘要翻译： 通过使用非常薄的氮化物抛光停止层例如不厚于400来消除或显着降低STI纹线形成。 非常薄的氮化物抛光停止层在随后的掩模，注入和清洁步骤中保持就位以形成掺杂剂区域，并且在栅极氧化物和栅电极形成之前被去除。