公开(公告)号：US07732336B2

公开(公告)日：2010-06-08

申请号：US12115473

申请日：2008-05-05

Applicant: Qi Xiang ,  James N. Pan ,  Jung-Suk Goo

Inventor： Qi Xiang ,  James N. Pan ,  Jung-Suk Goo

IPC: H01L21/311

CPC classification number: H01L29/66742 ,  H01L21/76283 ,  H01L29/458 ,  H01L29/7842 ,  H01L29/78687 ,  Y10S438/933

Abstract: A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The strained material is formed after the trench is formed. The process can be utilized on a compound semiconductor layer above a box layer.

Abstract translation: 集成电路（IC）的制造方法利用浅沟槽隔离（STI）技术。 浅沟槽隔离技术用于应变硅（SMOS）工艺。 在形成沟槽之后形成应变材料。 该方法可以用在盒层上方的化合物半导体层上。

公开(公告)号：US20080251851A1

公开(公告)日：2008-10-16

申请号：US11734673

申请日：2007-04-12

Applicant: James N. PAN ,  Sey-Ping SUN ,  Andrew M. WAITE

Inventor： James N. PAN ,  Sey-Ping SUN ,  Andrew M. WAITE

IPC: H01L21/8238 ,  H01L29/94

CPC classification number: H01L29/7843 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/517 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848 ,  H01L2924/0002 ,  Y10S438/938 ,  H01L2924/00

Abstract: A strain enhanced semiconductor device and methods for its fabrication are provided. One method comprises embedding a strain inducing semiconductor material in the source and drain regions of the device to induce a strain in the device channel. Thin metal silicide contacts are formed to the source and drain regions so as not to relieve the induced strain. A layer of conductive material is selectively deposited in contact with the thin metal silicide contacts, and metallized contacts are formed to the conductive material.

Abstract translation: 提供一种应变增强型半导体器件及其制造方法。 一种方法包括将应变诱导半导体材料嵌入在器件的源极和漏极区域中以在器件沟道中引起应变。 在源极和漏极区域形成薄金属硅化物触点，以免减轻诱发的应变。 选择性地沉积与薄金属硅化物触点接触的导电材料层，并且将金属化触点形成为导电材料。

公开(公告)号：US20080213952A1

公开(公告)日：2008-09-04

申请号：US12115473

申请日：2008-05-05

Applicant: Qi Xiang ,  James N. Pan ,  Jung-Suk Goo

Inventor： Qi Xiang ,  James N. Pan ,  Jung-Suk Goo

IPC: H01L21/762

CPC classification number: H01L29/66742 ,  H01L21/76283 ,  H01L29/458 ,  H01L29/7842 ,  H01L29/78687 ,  Y10S438/933

Abstract: A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The strained material is formed after the trench is formed. The process can be utilized on a compound semiconductor layer above a box layer.

Abstract translation: 集成电路（IC）的制造方法利用浅沟槽隔离（STI）技术。 浅沟槽隔离技术用于应变硅（SMOS）工艺。 在形成沟槽之后形成应变材料。 该方法可以用在盒层上方的化合物半导体层上。

公开(公告)号：US07033869B1

公开(公告)日：2006-04-25

申请号：US10755896

申请日：2004-01-13

Applicant: Qi Xiang ,  Jung-Suk Goo ,  James N. Pan

Inventor： Qi Xiang ,  Jung-Suk Goo ,  James N. Pan

IPC: H01L21/00 ,  H01L21/84 ,  H01L27/01 ,  H01L27/12

CPC classification number: H01L29/66545 ,  H01L29/4908 ,  H01L29/78687

Abstract: An SOI substrate comprises a layer of strained silicon sandwiched between a dielectric layer and a layer of strained silicon. The substrate may be used to form a strained silicon SOI MOSFET having a gate electrode that extends through the silicon germanium layer to a channel region formed in the strained silicon layer. The MOSFET may be formed in a fully depleted state by using a strained silicon layer of appropriate thickness.

Abstract translation: SOI衬底包括夹在电介质层和应变硅层之间的应变层的层。 衬底可以用于形成具有延伸穿过硅锗层的栅电极到形成在应变硅层中的沟道区的应变硅SOI MOSFET。 可以通过使用适当厚度的应变硅层，在完全耗尽状态下形成MOSFET。

公开(公告)号：US06936516B1

公开(公告)日：2005-08-30

申请号：US10755811

申请日：2004-01-12

Applicant: Jung-Suk Goo ,  Qi Xiang ,  James N. Pan

Inventor： Jung-Suk Goo ,  Qi Xiang ,  James N. Pan

IPC: H01L21/00 ,  H01L21/336 ,  H01L29/10 ,  H01L29/786

CPC classification number: H01L29/785 ,  H01L29/1054 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78687

Abstract: An exemplary embodiment relates to a method of FinFET formation. The method can include providing a sacrificial fin structure, removing the sacrificial fin structure, and providing a strained silicon layer at the location of the removed sacrificial gate structure. The FinFET can include a strained-Si MOSFET channel region.

Abstract translation: 示例性实施例涉及FinFET形成的方法。 该方法可以包括提供牺牲鳍结构，去除牺牲鳍结构，以及在去除的牺牲栅结构的位置处提供应变硅层。 FinFET可以包括应变Si MOSFET沟道区域。

公开(公告)号：US06929992B1

公开(公告)日：2005-08-16

申请号：US10738496

申请日：2003-12-17

Applicant: Ihsan J. Djomehri ,  Qi Xiang ,  Jung-Suk Goo ,  James N. Pan

Inventor： Ihsan J. Djomehri ,  Qi Xiang ,  Jung-Suk Goo ,  James N. Pan

IPC: H01L21/28 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12 ,  H01L29/49 ,  H01L29/786

CPC classification number: H01L21/823842 ,  H01L21/28097 ,  H01L21/823807 ,  H01L21/823835 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/4908 ,  H01L29/785 ,  H01L29/78687

Abstract: The threshold voltage shift exhibited by strained silicon NMOS devices is compensated with respect to the threshold voltages of PMOS devices formed on the same substrate by increasing the work function of the NMOS gates. The NMOS gate work function exceeds the PMOS gate work function so as to compensate for a difference in the respective NMOS and PMOS threshold voltages. The NMOS gates are preferably fully silicided while the PMOS gates are partially silicided.

Abstract translation: 通过增加NMOS栅极的功函数，相对于在同一衬底上形成的PMOS器件的阈值电压补偿由应变硅NMOS器件表现出的阈值电压漂移。 NMOS栅极功能超过PMOS栅极功能，以补偿各个NMOS和PMOS阈值电压的差异。 NMOS栅极优选是完全硅化的，而PMOS栅极部分地被硅化。

公开(公告)号：US07138302B2

公开(公告)日：2006-11-21

申请号：US10755763

申请日：2004-01-12

Applicant: Qi Xiang ,  James N. Pan ,  Jung-Suk Goo

Inventor： Qi Xiang ,  James N. Pan ,  Jung-Suk Goo

IPC: H01L21/335 ,  H01L21/84 ,  H01L21/338 ,  H01L21/8249 ,  H01L27/01

CPC classification number: H01L29/785 ,  H01L29/66795 ,  H01L29/7842

Abstract: An exemplary embodiment relates to a method of FinFET channel structure formation. The method can include providing a compound semiconductor layer above an insulating layer, providing a trench in the compound semiconductor layer, and providing a strained semiconductor layer above the compound semiconductor layer and within the trench. The method can also include removing the strained semiconductor layer from above the compound semiconductor layer, thereby leaving the strained semiconductor layer within the trench and removing the compound semiconductor layer to leave the strained semiconductor layer and form the fin-shaped channel region.

Abstract translation: 示例性实施例涉及FinFET沟道结构形成的方法。 该方法可以包括在绝缘层之上提供化合物半导体层，在化合物半导体层中提供沟槽，并在化合物半导体层之上和沟槽内提供应变半导体层。 该方法还可以包括从化合物半导体层上方去除应变半导体层，从而将应变半导体层留在沟槽内，并去除化合物半导体层以留下应变半导体层并形成鳍状沟道区。

公开(公告)号：US07078299B2

公开(公告)日：2006-07-18

申请号：US10654631

申请日：2003-09-03

Applicant: Witold P. Maszara ,  Jung-Suk Goo ,  James N. Pan ,  Qi Xiang

Inventor： Witold P. Maszara ,  Jung-Suk Goo ,  James N. Pan ,  Qi Xiang

IPC: H01L21/336

CPC classification number: H01L29/785 ,  A61F5/3776 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/78687 ,  Y10S438/933

Abstract: A method of forming a finFET transistor using a sidewall epitaxial layer includes forming a silicon germanium (SiGe) layer above an oxide layer above a substrate, forming a cap layer above the SiGe layer, removing portions of the SiGe layer and the cap layer to form a feature, forming sidewalls along lateral walls of the feature, and removing the feature.

Abstract translation: 使用侧壁外延层形成finFET晶体管的方法包括在衬底上方的氧化层上形成硅锗（SiGe）层，在SiGe层上方形成覆盖层，去除SiGe层和覆盖层的部分以形成 特征，沿着所述特征的侧壁形成侧壁，以及去除所述特征。

公开(公告)号：US07074657B2

公开(公告)日：2006-07-11

申请号：US10706948

申请日：2003-11-14

Applicant: James N. Pan ,  John G. Pellerin ,  Jon Cheek

Inventor： James N. Pan ,  John G. Pellerin ,  Jon Cheek

IPC: H01L21/336

CPC classification number: H01L29/78696 ,  H01L29/78639

Abstract: A multiple-channel semiconductor device has fully or partially depleted quantum wells and is especially useful in ultra large scale integration devices, such as CMOSFETs. Multiple channel regions are provided on a substrate with a gate electrode formed on the uppermost channel region, separated by a gate oxide, for example. The vertical stacking of multiple channels and the gate electrode permit increased drive current in a semiconductor device without increasing the silicon area occupied by the device.

Abstract translation: 多通道半导体器件具有完全或部分耗尽的量子阱，并且在超大规模集成器件（例如CMOSFET）中特别有用。 多个通道区域设置在基板上，其栅电极形成在最上通道区域上，例如由栅极氧化物分隔开。 多通道和栅电极的垂直堆叠允许增加半导体器件中的驱动电流，而不增加器件占用的硅面积。

公开(公告)号：US07045384B1

公开(公告)日：2006-05-16

申请号：US10614031

申请日：2003-07-08

Applicant: James N. Pan ,  Christy Mei-Chu Woo

Inventor： James N. Pan ,  Christy Mei-Chu Woo

IPC: H01L21/00

CPC classification number: H01L29/66143 ,  G01R31/2831

Abstract: A method of determining a work function of a metal to be used as a metal gate material provides a metal-on-silicon (MS) Schottky diode on a silicon substrate. The MS Schottky diode is formed by deposition of the metal in a single step deposition through a shadow mask that is secured on the silicon substrate.

Abstract translation: 确定用作金属栅极材料的金属的功函数的方法在硅衬底上提供硅上金属（MS）肖特基二极管。 MS肖特基二极管通过在单个步骤沉积中沉积金属形成，该阴影掩模固定在硅衬底上。