公开(公告)号：US06300205B1

公开(公告)日：2001-10-09

申请号：US09193262

申请日：1998-11-18

申请人： H. Jim Fulford ,  Jon Cheek ,  Derick J. Wristers ,  James Buller

发明人： H. Jim Fulford ,  Jon Cheek ,  Derick J. Wristers ,  James Buller

IPC分类号： H01L21336

CPC分类号： H01L29/6653 ,  H01L21/26586 ,  H01L29/1083 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： One method of making a semiconductor device includes forming a gate electrode on a substrate and forming a spacer on a sidewall of the gate electrode. An active region is then formed in the substrate and adjacent to the spacer, but spaced apart from the gate electrode, using a first dopant material. A halo region is formed in the substrate under the spacer and adjacent to the active region using a second dopant material of a conductivity type different than the first dopant material. The halo region may be formed by implanting the second dopant region into the substrate at an angle substantially less than 90° relative to a surface of the substrate. A portion of the spacer is then removed and a lightly-doped region is formed in the substrate adjacent to the active region and the gate electrode and shallower than the halo region using a third dopant material of a same conductivity type as the first dopant material.

摘要翻译： 制造半导体器件的一种方法包括在衬底上形成栅电极并在栅电极的侧壁上形成间隔物。 然后，使用第一掺杂剂材料，在衬底中形成有源区并与间隔物相邻，但与栅电极间隔开。 使用不同于第一掺杂剂材料的导电类型的第二掺杂剂材料，在间隔物下方的衬底中形成晕圈区域并与有源区相邻。 可以通过相对于衬底的表面以相对小于90°的角度将第二掺杂剂区域注入到衬底中来形成晕圈区域。 然后去除间隔物的一部分，并且使用与第一掺杂剂材料相同的导电类型的第三掺杂剂材料，在邻近有源区和栅电极的衬底中形成轻掺杂区域，并且比晕区浅。

公开(公告)号：US6114211A

公开(公告)日：2000-09-05

申请号：US195336

申请日：1998-11-18

申请人： H. Jim Fulford ,  Jon Cheek ,  Derick J. Wristers ,  James Buller

发明人： H. Jim Fulford ,  Jon Cheek ,  Derick J. Wristers ,  James Buller

IPC分类号： H01L21/336 ,  H01L29/10

CPC分类号： H01L29/66492 ,  H01L29/1083 ,  H01L29/6653 ,  H01L29/6659

摘要： One method of forming a semiconductor device includes forming a gate electrode on a substrate and then forming a spacer adjacent to a sidewall of the gate electrode. An active region is formed in the substrate adjacent to the spacer and spaced apart from the gate electrode using a first dopant material of a first conductivity type. A protecting layer is formed over the active region and adjacent to the spacer. At least a portion of the spacer is then removed to form an opening between the protecting layer and the gate electrode. In some instances, the spacer may be formed by independent deposition of two different materials (e.g., silicon nitride and silicon dioxide), one of which can be selectively removed with respect to the other. A lightly-doped region is formed in the substrate adjacent to the gate electrode using a second dopant material of the first conductivity type. This lightly-doped region may be formed, for example, prior to formation of the spacer, between the formation of two portions of the spacer, or after removing at least a portion of the spacer. A halo region is formed through the opening resulting from removing a portion of the spacer. The halo region is deeper in the substrate than the lightly-doped region and is adjacent to the active region. The halo region is formed using a third dopant material of a conductivity type different than the first conductivity type.

摘要翻译： 形成半导体器件的一种方法包括在衬底上形成栅电极，然后形成与栅电极的侧壁相邻的间隔物。 使用第一导电类型的第一掺杂剂材料，在与衬垫相邻的衬底中形成有源区，并与栅电极间隔开。 保护层形成在有源区上并与隔片相邻。 然后去除间隔物的至少一部分以在保护层和栅电极之间形成开口。 在一些情况下，可以通过独立沉积两种不同材料（例如，氮化硅和二氧化硅）来形成隔离物，其中一种可以相对于另一种材料选择性地去除。 使用第一导电类型的第二掺杂剂材料在与栅电极相邻的衬底中形成轻掺杂区域。 该轻掺杂区域例如可以在形成间隔物之前，在间隔物的两个部分的形成之间或在移除间隔物的至少一部分之后形成。 通过从隔离物的一部分去除而形成的晕圈形成。 卤素区域在衬底中比轻掺杂区域更深，并且与有源区域相邻。 卤素区域是使用不同于第一导电类型的导电类型的第三掺杂剂材料形成的。

公开(公告)号：US6074906A

公开(公告)日：2000-06-13

申请号：US958534

申请日：1997-10-27

申请人： Jon Cheek ,  Derick J. Wristers ,  H. Jim Fulford

发明人： Jon Cheek ,  Derick J. Wristers ,  H. Jim Fulford

IPC分类号： H01L21/8238

CPC分类号： H01L21/823864

摘要： A CMOS semiconductor device having NMOS source/drain regions formed using multiple spacers has at least one NMOS region and at least one PMOS region. A first n-type dopant is selectively implanted into an NMOS active region of the substrate adjacent a NMOS gate electrode to form a first n-doped region in the NMOS active region. A first NMOS spacer is formed on a sidewall of the NMOS gate electrode and a first PMOS spacer on a sidewall of a PMOS gate electrode. A second n-type dopant is selectively implanted into the NMOS active region using the first NMOS spacer as a mask. A p-type dopant is selectively implanted into a PMOS active region using the first PMOS spacer as a mask to form a first p-doped region in the PMOS active region. A second NMOS spacer and a second PMOS spacer are formed adjacent the first NMOS spacer and first PMOS spacer, respectively. A third n-type dopant is selectively implanted into the NMOS active region using the second NMOS spacer as a mask to form a third n-doped region deeper than the second n-doped region in the NMOS active region. A second p-type dopant is selectively implanted into the PMOS active region using the second PMOS spacer as a mask to form a second p-doped region in the PMOS active region deeper than the first p-doped region.

摘要翻译： 具有使用多个间隔物形成的NMOS源极/漏极区域的CMOS半导体器件具有至少一个NMOS区域和至少一个PMOS区域。 第一n型掺杂剂被选择性地注入到与NMOS栅电极相邻的衬底的NMOS有源区中，以在NMOS有源区中形成第一n掺杂区。 第一NMOS间隔物形成在NMOS栅电极的侧壁和PMOS栅电极的侧壁上的第一PMOS间隔物上。 使用第一NMOS间隔物作为掩模，将第二n型掺杂剂选择性地注入NMOS有源区。 使用第一PMOS间隔物作为掩模将p型掺杂剂选择性地注入PMOS有源区，以在PMOS有源区中形成第一p掺杂区。 分别与第一NMOS间隔物和第一PMOS间隔物相邻地形成第二NMOS间隔物和第二PMOS间隔物。 使用第二NMOS间隔物作为掩模，将第三n型掺杂剂选择性地注入NMOS有源区，以形成比NMOS有源区中的第二n掺杂区更深的第三n掺杂区。 使用第二PMOS间隔物作为掩模将第二p型掺杂剂选择性地注入到PMOS有源区中，以在PMOS有源区中形成比第一p掺杂区更深的第二p掺杂区。

公开(公告)号：US06979878B1

公开(公告)日：2005-12-27

申请号：US09217213

申请日：1998-12-21

申请人： Mark I. Gardner ,  H. Jim Fulford ,  Derick J. Wristers

发明人： Mark I. Gardner ,  H. Jim Fulford ,  Derick J. Wristers

IPC分类号： H01L21/762 ,  H01L29/36

CPC分类号： H01L21/76237

摘要： A method for isolating a first active region from a second active region, both of which are configured within a semiconductor substrate. The method comprises forming a dielectric masking layer above a semiconductor substrate. An opening is then formed through the masking layer. A pair of dielectric spacers are formed upon the sidewalls of the masking layer within the opening. A trench is then etched in the semiconductor substrate between the dielectric spacers. A first dielectric layer is then thermally grown on the walls and base of the trench. A CVD oxide is deposited into the trench and processed such that the upper surface of the CVD oxide is commensurate with the substrate surface. Portions of the spacers are also removed such that the thickness of the spacers is between about 0 to 200 Å. Silicon atoms and/or barrier atoms, such as nitrogen atoms, are then implanted ino regions of the active areas in close proximity to the trench isolation structure.

摘要翻译： 一种用于将第一有源区与第二有源区隔离的方法，二者均配置在半导体衬底内。 该方法包括在半导体衬底上形成电介质掩模层。 然后通过掩模层形成开口。 在开口内的掩模层的侧壁上形成一对电介质隔离物。 然后在电介质间隔物之间​​的半导体衬底中蚀刻沟槽。 然后在沟槽的壁和基底上热生长第一介电层。 将CVD氧化物沉积到沟槽中并进行处理，使得CVD氧化物的上表面与衬底表面相当。 间隔物的一部分也被去除，使得间隔物的厚度在约0至200埃之间。 然后将硅原子和/或势垒原子（例如氮原子）注入非常靠近沟槽隔离结构的有源区的多个区域中。

公开(公告)号：US06258646B1

公开(公告)日：2001-07-10

申请号：US09149631

申请日：1998-09-08

申请人： H. Jim Fulford, Jr. ,  Mark I. Gardner ,  Derick J. Wristers

发明人： H. Jim Fulford, Jr. ,  Mark I. Gardner ,  Derick J. Wristers

IPC分类号： H01L218238

CPC分类号： H01L27/092 ,  H01L21/823814 ,  Y10S257/90

摘要： A transistor and a transistor fabrication method for forming an LDD structure in which the n-type dopants associated with an n-channel transistor are formed prior to the formation of the p-type dopants is presented. The n-type source/drain and LDD implants generally require higher activation energy (thermal anneal) than the p-type source/drain and LDD implants. The n-type arsenic source/drain implant, which has the lowest diffusivity and requires the highest temperature anneal, is performed first in the LDD process formation. Performing such a high temperature anneal first ensures minimum additional migration of subsequent, more mobile implants. Mobile implants associated with lighter and less dense implant species are prevalent in LDD areas near the channel perimeter. The likelihood of those implants moving into the channel is lessened by tailoring subsequent anneal steps to temperatures less than the source/drain anneal step.

摘要翻译： 提出一种用于形成LDD结构的晶体管和晶体管制造方法，其中在形成p型掺杂剂之前形成与n沟道晶体管相关联的n型掺杂剂。 n型源极/漏极和LDD植入物通常需要比p型源极/漏极和LDD植入物更高的活化能（热退火）。 首先在LDD工艺形成中执行具有最低扩散率并且需要最高温度退火的n型砷源/漏极注入。 首先进行这样的高温退火可确保随后的更多移动式植入物的最小额外迁移。 与更轻和较不密集的种植体物种相关的移植植入物在通道周边附近的LDD区域是普遍的。 通过将后续退火步骤调整到低于源极/漏极退火步骤的温度，使得这些植入物进入通道的可能性降低。

公开(公告)号：US06188114B1

公开(公告)日：2001-02-13

申请号：US09204016

申请日：1998-12-01

申请人： Mark I. Gardner ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Frederick N. Hause ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

发明人： Mark I. Gardner ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Frederick N. Hause ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

IPC分类号： H01L31119

CPC分类号： H01L29/41783 ,  H01L29/41775 ,  H01L29/66575 ,  H01L29/6659

摘要： An IGFET with metal spacers is disclosed. The IGFET includes a gate electrode on a gate insulator on a semiconductor substrate. Sidewall insulators are adjacent to opposing vertical edges of the gate electrode, and metal spacers are formed on the substrate and adjacent to the sidewall insulators. The metal spacers are electrically isolated from the gate electrode but contact portions of the drain and the source. Preferably, the metal spacers are adjacent to edges of the gate insulator beneath the sidewall insulators. The metal spacers are formed by depositing a metal layer over the substrate then applying an anisotropic etch. In one embodiment, the metal spacers contact lightly and heavily doped drain and source regions, thereby increasing the conductivity between the heavily doped drain and source regions and the channel underlying the gate electrode. The metal spacers can also provide low resistance drain and source contacts.

摘要翻译： 公开了具有金属间隔物的IGFET。 IGFET在半导体衬底上的栅极绝缘体上包括栅电极。 侧壁绝缘体与栅电极的相对的垂直边缘相邻，并且金属间隔件形成在衬底上并且与侧壁绝缘体相邻。 金属间隔物与栅电极电绝缘，但是漏极和源极的接触部分。 优选地，金属间隔件邻近侧壁绝缘体之下的栅极绝缘体的边缘。 通过在衬底上沉积金属层然后施加各向异性蚀刻来形成金属间隔物。 在一个实施例中，金属间隔物接触轻掺杂和重掺杂的漏极和源极区域，从而增加重掺杂漏极和源极区域之间的导电性以及栅电极下面的沟道。 金属间隔物还可以提供低电阻漏极和源极触点。

公开(公告)号：US6166354A

公开(公告)日：2000-12-26

申请号：US876381

申请日：1997-06-16

申请人： Frederick N. Hause ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Mark I. Gardner ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

发明人： Frederick N. Hause ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Mark I. Gardner ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

IPC分类号： C30B31/12 ,  C30B31/18 ,  F27B5/14

CPC分类号： C30B31/18 ,  C30B31/12

摘要： An optical monitoring of electrical characteristics of devices in a semiconductor is performed during an anneal step to detect the time annealing is complete and activation occurs. A surface photovoltage measurement is made during annealing to monitor the charge state on the surface of a substrate wafer to determine when the substrate is fully annealed. The surface photovoltage measurement is monitored, the time of annealing is detected, and a selected over-anneal is controlled. The surface photovoltage (SPV) measurement is performed to determine a point at which a dopant or impurity such as boron or phosphorus is annealed in a silicon lattice. In some embodiments, the point of detection is used as a feedback signal in an RTA annealing system to adjust a bank of annealing lamps for annealing and activation uniformity control. The point of detection is also used to terminate the annealing process to minimize D.sub.t.

摘要翻译： 在退火步骤期间执行半导体器件的电特性的光学监测，以检测时间退火完成并发生激活。 在退火期间进行表面光电压测量以监测衬底晶片的表面上的电荷状态，以确定衬底何时完全退火。 监测表面光电压测量，检测退火时间，并控制所选择的过退火。 执行表面光电压（SPV）测量以确定在硅晶格中退火掺杂剂或杂质如硼或磷的点。 在一些实施例中，将检测点用作RTA退火系统中的反馈信号，以调整用于退火和激活均匀性控制的退火灯组。 检测点也用于终止退火过程以最小化Dt。

公开(公告)号：US6162688A

公开(公告)日：2000-12-19

申请号：US231427

申请日：1999-01-14

申请人： Mark I. Gardner ,  H. Jim Fulford ,  Derick J. Wristers

发明人： Mark I. Gardner ,  H. Jim Fulford ,  Derick J. Wristers

IPC分类号： H01L21/266 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/06 ,  H01L29/49 ,  H01L29/51 ,  H01L29/786 ,  H01L21/00

CPC分类号： H01L21/28194 ,  H01L21/266 ,  H01L21/268 ,  H01L21/28158 ,  H01L21/28202 ,  H01L21/823842 ,  H01L27/0688 ,  H01L29/4908 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/66757 ,  H01L29/78636

摘要： A method is provided for fabricating a transistor, the method including forming a dielectric layer above a structure, forming a first polysilicon layer above the dielectric layer and forming a sacrificial region above the first polysilicon layer. The method also includes forming a second polysilicon layer above the first polysilicon layer and adjacent the sacrificial region. The method further includes removing the sacrificial region to form an opening in the second polysilicon layer, the opening having sidewalls, and forming dielectric spacers on the sidewalls of the opening. In addition, the method includes forming a gate dielectric within the opening above the first polysilicon layer and forming a gate conductor above the gate dielectric.

摘要翻译： 提供了一种用于制造晶体管的方法，所述方法包括在结构之上形成电介质层，在电介质层上方形成第一多晶硅层，并在第一多晶硅层上方形成牺牲区域。 该方法还包括在第一多晶硅层上形成第二多晶硅层并且邻近牺牲区。 该方法还包括去除牺牲区域以在第二多晶硅层中形成开口，该开口具有侧壁，并在开口的侧壁上形成电介质间隔物。 此外，该方法包括在第一多晶硅层上方的开口内形成栅极电介质，并在栅极电介质上方形成栅极导体。

公开(公告)号：US6146978A

公开(公告)日：2000-11-14

申请号：US73639

申请日：1998-05-06

申请人： Mark W. Michael ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Mark I. Gardner ,  Frederick N. Hause ,  Bradley T. Moore ,  Derick J. Wristers

发明人： Mark W. Michael ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Mark I. Gardner ,  Frederick N. Hause ,  Bradley T. Moore ,  Derick J. Wristers

IPC分类号： H01L21/768 ,  H01L21/8238 ,  H01L21/44 ,  H01L21/4763 ,  H01L31/119

CPC分类号： H01L21/823871 ,  H01L21/76802 ,  H01L21/76895

摘要： An interlevel interconnect is formed in a window opened through an isolation layer and through an etch barrier to expose an electrode surface and an adjacent isolation barrier. The interlevel interconnect may be disposed on substantially all of a portion of the underlying electrode such as an insulated gate field effect transistor (IGFET) source/drain region surface. The etch barrier provides controlled etching to allow for overlap of the interlevel interconnect onto the isolation barrier without increased parasitic capacitance relative to conventional contact misalignments. Furthermore, allaying concerns of overlapping allows for increased utilization of source/drain region surface area by the interlevel interconnect. Furthermore, the etch barrier allows the interlevel interconnect to strap electrodes of a plurality of circuit devices while exhibiting nominal if any substrate to interlevel interconnect leakage currents.

摘要翻译： 在通过隔离层打开的窗口中并通过蚀刻屏障形成层间互连，以露出电极表面和相邻隔离屏障。 层间互连可以布置在底层电极的基本上全部的一部分上，例如绝缘栅场效应晶体管（IGFET）源/漏区表面。 蚀刻屏障提供受控的蚀刻，以允许层间互连重叠在隔离屏障上，而不增加寄生电容，相对于传统的接触不对准。 此外，消除重叠的关注允许通过层间互连增加源/漏区表面积的利用。 此外，蚀刻屏障允许层间互连以多个电路器件的带状电极同时显示标称的任何衬底以互连互连漏电流。

公开(公告)号：US6104063A

公开(公告)日：2000-08-15

申请号：US942998

申请日：1997-10-02

申请人： H. Jim Fulford, Jr. ,  Mark I. Gardner ,  Derick J. Wristers

发明人： H. Jim Fulford, Jr. ,  Mark I. Gardner ,  Derick J. Wristers

IPC分类号： H01L21/336 ,  H01L29/78 ,  H01L29/76 ,  H01L27/088

CPC分类号： H01L29/66492 ,  H01L29/6659 ,  H01L29/7833 ,  Y10S257/90

摘要： A transistor and a transistor fabrication method are presented where a sequence of spacers are formed and partially removed upon sidewall surfaces of the gate conductor to produce a graded junction having a relatively smooth doping profile. The spacers include removable and non-removable structures formed on the sidewall surfaces. The adjacent structures have dissimilar etch characteristics compared to each other and compared to the gate conductor. A first dopant (MDD dopant) and a second dopant (source/drain dopant) are implanted into the semiconductor substrate after the respective formation of the removable structure and the non-removable structure. A third dopant (LDD dopant) is implanted into the semiconductor substrate after the removable layer is removed from between the gate conductor and the non-removable structure (spacer). As a result a graded junction is created having higher concentration regions formed outside of lightly concentration regions, relative to the channel area. Such a doping profile provides superior protection against the hot-carrier effect compared to the traditional LDD structure. The smoother the doping profile, the more gradual the voltage drop across the channel/drain junction. A more gradual voltage drop gives rise to a smaller electric field and reduces the hot-carrier effect. Furthermore, the MDD and source/drain implants are performed first, prior to the LDD implant. This allows high-temperature thermal anneals to be performed first, followed by lower temperature anneals second.

摘要翻译： 提出了晶体管和晶体管制造方法，其中在栅极导体的侧壁表面上形成并部分地去除间隔物序列，以产生具有相对平滑的掺杂分布的梯度结。 间隔件包括形成在侧壁表面上的可移除和不可移除的结构。 相邻的结构具有彼此相比的不同的蚀刻特性并且与栅极导体相比较。 在可移除结构和不可移除结构的相应形成之后，将第一掺杂剂（MDD掺杂剂）和第二掺杂剂（源极/漏极掺杂剂）注入到半导体衬底中。 在可移除层从栅极导体和不可移除结构（间隔物）之间移除之后，将第三掺杂剂（LDD掺杂剂）注入到半导体衬底中。 结果，相对于通道面积产生了在轻微浓度区域之外形成的具有较高浓度区域的分级结。 与传统的LDD结构相比，这种掺杂分布提供了优于热载体效应的保护。 掺杂曲线越平滑，通道/漏极结上的电压降越低。 更加缓慢的电压降会导致较小的电场并降低热载流子效应。 此外，在LDD植入之前，首先执行MDD和源/漏植入。 这允许首先执行高温热退火，其次是较低的温度退火。