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11.发明授权Implanted hidden interconnections in a semiconductor device for preventing reverse engineering 有权在半导体器件中隐藏的互连用于防止逆向工程公开(公告)号：US07166515B2
公开(公告)日：2007-01-23
申请号：US10132523
申请日：2002-04-24
IPC分类号： H01L21/336
CPC分类号： H01L27/02 , H01L21/743
摘要： A camouflaged interconnection for interconnecting two spaced-apart regions of a common conductivity type in an integrated circuit or device and a method of forming same. The camouflaged interconnection comprises a first region forming a conducting channel between the two spaced-apart regions, the conducting channel being of the same common conductivity type and bridging a region between the two spaced-apart regions, and a second region of opposite conductivity to type, the second region being disposed between the two spaced-apart regions of common conductivity type and over lying the conducting channel to camouflage the conducting channel from reverse engineering.
摘要翻译： 用于在集成电路或器件中互连公共导电类型的两个间隔开的区域的伪装互连和其形成方法。 伪装的互连包括在两个间隔开的区域之间形成导电通道的第一区域，导电沟道具有相同的共同导电类型并桥接两个间隔开的区域之间的区域，以及与类型相反的导电性的第二区域 所述第二区域设置在所述公共导电类型的两个间隔开的区域之间，并且位于所述导电通道上以伪装所述导电通道以进行逆向工程。
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12.发明授权Permanently on transistor implemented using a double polysilicon layer CMOS process with buried contact 失效永久性地使用采用双重多晶硅层CMOS工艺的埋入触点实现晶体管公开(公告)号：US06919600B2
公开(公告)日：2005-07-19
申请号：US10789261
申请日：2004-02-26
IPC分类号： H01L21/768 , H01L21/8234 , H01L23/58 , H01L27/088 , H01L29/78 , H01L21/8238 , H01L29/76
CPC分类号： H01L27/0203 , H01L21/76895 , H01L21/823462 , H01L23/576 , H01L27/0883 , H01L29/7834 , H01L2924/0002 , Y10S257/922 , H01L2924/00
摘要： A permanently-ON MOS transistor comprises silicon source and drain regions of a first conductivity type in a silicon well region of a second conductivity type. A silicon contact region of the first conductivity types is buried in the well region, said contact region contacting said source region and said drain region. A first gate insulating layer is selectively placed over the silicon source and drain regions. A second gate insulating layer is selectively placed over the first gate insulating layer and over the silicon contact region. A polysilicon gate region is placed over the second gate insulating layer.
摘要翻译： 永久导通MOS晶体管包括在第二导电类型的硅阱区域中的第一导电类型的硅源极和漏极区域。 所述第一导电类型的硅接触区域埋在所述阱区域中，所述接触区域接触所述源极区域和所述漏极区域。 选择性地将第一栅极绝缘层放置在硅源极和漏极区域上。 第二栅极绝缘层选择性地放置在第一栅极绝缘层上方和硅接触区域上。 多晶硅栅极区域放置在第二栅极绝缘层上。
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公开(公告)号：US06774413B2
公开(公告)日：2004-08-10
申请号：US09882900
申请日：2001-06-15
IPC分类号： H01L2710
CPC分类号： H01L27/02 , H01L21/76895 , H01L23/573 , H01L27/0203
摘要： An integrated circuit structure for MOS-type devices including a silicon substrate of a first conductivity type; a first gate insulating regions selectively placed over the silicon substrate of the first conductivity type; a first polycrystalline silicon layer selectively placed over the silicon substrate of the first conductivity type; a second gate insulating regions selectively placed over the first gate insulating regions and the first polycrystalline silicon layer; a second polycrystalline silicon layer selectively placed over the second gate insulating regions; first buried silicon regions of a second conductivity type, buried within the silicon substrate of the first conductivity type, placed under the first polycrystalline silicon layer and in contact therewith; and second buried silicon regions of the second conductivity type, buried within the silicon substrate of the first conductivity type, placed under the second gate insulating regions, under the second polycrystalline silicon layer and insulated therefrom.
摘要翻译： 一种用于包括第一导电类型的硅衬底的MOS器件的集成电路结构; 选择性地放置在第一导电类型的硅衬底上的第一栅绝缘区; 选择性地放置在第一导电类型的硅衬底上的第一多晶硅层; 选择性地放置在所述第一栅极绝缘区域和所述第一多晶硅层上的第二栅极绝缘区域; 选择性地放置在所述第二栅极绝缘区域上的第二多晶硅层; 埋在第一导电类型的硅衬底内的第二导电类型的第一掩埋硅区域放置在第一多晶硅层下方并与其接触; 以及第二导电类型的第二掩埋硅区域，埋在第一导电类型的硅衬底内，放置在第二栅极绝缘区域下方，在第二多晶硅层下方并与其绝缘。
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14.发明授权Method and apparatus using silicide layer for protecting integrated circuits from reverse engineering 有权使用硅化物层保护集成电路免于逆向工程的方法和装置
公开(公告)号：US6117762A
公开(公告)日：2000-09-12
申请号：US298293
申请日：1999-04-23
IPC分类号： H01L21/28 , H01L21/285 , H01L21/3205 , H01L21/768 , H01L21/822 , H01L21/8238 , H01L23/52 , H01L27/02 , H01L27/04 , H01L27/092 , H01L21/4763
CPC分类号： H01L23/573 , H01L21/28518 , H01L21/76895 , H01L21/823835 , H01L27/02 , H01L2924/0002
摘要： A method and apparatus for protecting semiconductor integrated circuits from reverse engineering. Semiconductor active areas are formed on a substrate. A silicide layer is formed both over at least one active area of the semiconductor active areas and over a selected substrate area for interconnecting the at least one active area with another area through the silicide area formed on the selected substrate area. In a preferred embodiment a silicide layer formed on a first active area is interconnectingly merged laterally with a silicide layer formed on a second active area through the silicide layer formed on the selected substrate area.
摘要翻译： 一种用于保护半导体集成电路免于逆向工程的方法和装置。 半导体有源区形成在基板上。 在半导体有源区域的至少一个有效区域上方以及选定的衬底区域上形成硅化物层，用于通过形成在所选择的衬底区域上的硅化物区域将至少一个有源区域与另一区域互连。 在优选实施例中，形成在第一有源区上的硅化物层与通过形成在所选择的衬底区域上的硅化物层形成在第二有源区上的硅化物层横向地相互合并。
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15.发明授权
公开(公告)号：US5930663A
公开(公告)日：1999-07-27
申请号：US76012
申请日：1998-05-11
IPC分类号： H01L21/3205 , G06F21/06 , G11C7/24 , H01L21/82 , H01L21/822 , H01L23/52 , H01L27/02 , H01L27/04 , H01L21/265
CPC分类号： H01L23/573 , G11C7/24 , H01L27/02 , H01L2924/0002
摘要： An integrated digital circuit is protected from reverse engineering by fabricating all transistors of like conductivity with a common size and geometric layout, providing a common layout for different logic cells, connecting doped circuit elements of like conductivity with electrically conductive doped implants in the substrate rather than metalized interconnections, and providing non-functional apparent interconnections that are interrupted by non-discernable channel stops so that all cells falsely appear to have a common interconnection scheme. The camouflage is enhanced by providing a uniform pattern of metal leads over the transistor array, with a uniform pattern of heavily doped implant taps from the transistors for connection to the leads; undesired tap-lead connections are blocked by channel stops.
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16.发明授权Conductive channel pseudo block process and circuit to inhibit reverse engineering 失效导电通道伪块处理和电路抑制反向工程公开(公告)号：US08258583B1
公开(公告)日：2012-09-04
申请号：US12949657
申请日：2010-11-18
IPC分类号： H01L27/088
CPC分类号： H01L27/0203 , G06K19/073 , G06K19/07363 , H01L23/573 , H01L2924/0002 , H01L2924/00
摘要： A technique for and structures for camouflaging an integrated circuit structure. The integrated circuit structure is formed by a plurality of layers of material having a controlled outline. A layer of conductive material having a controlled outline is disposed among said plurality of layers to provide artifact edges of the conductive material that resemble one type of transistor (operable vs. non-operable), when in fact another type of transistor was used.
摘要翻译： 用于伪装集成电路结构的技术和结构。 集成电路结构由具有受控轮廓的多层材料形成。 具有受控轮廓的导电材料层设置在所述多个层中，以提供类似于一种类型的晶体管（可操作与不可操作的）的导电材料的伪影边缘，当实际上使用另一种类型的晶体管时。
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17.发明授权Conductive channel pseudo block process and circuit to inhibit reverse engineering 有权导电通道伪块处理和电路抑制逆向工程公开(公告)号：US07888213B2
公开(公告)日：2011-02-15
申请号：US11375846
申请日：2006-03-14
IPC分类号： H01L21/8236
CPC分类号： H01L27/0203 , G06K19/073 , G06K19/07363 , H01L23/573 , H01L2924/0002 , H01L2924/00
摘要： A technique for and structures for camouflaging an integrated circuit structure. The integrated circuit structure is formed by a plurality of layers of material having a controlled outline. A layer of conductive material having a controlled outline is disposed among said plurality of layers to provide artifact edges of the conductive material that resemble one type of transistor (operable vs. non-operable), when in fact another type of transistor was used.
摘要翻译： 用于伪装集成电路结构的技术和结构。 集成电路结构由具有受控轮廓的多层材料形成。 具有受控轮廓的导电材料层设置在所述多个层中，以提供类似于一种类型的晶体管（可操作与不可操作的）的导电材料的伪影边缘，当实际上使用另一种类型的晶体管时。
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公开(公告)号：US07514755B2
公开(公告)日：2009-04-07
申请号：US10735841
申请日：2003-12-12
IPC分类号： H01L29/76
CPC分类号： H01L21/823892 , H01L27/02
摘要： A technique for and structures for camouflaging an integrated circuit structure. The integrated circuit structure is formed having a well of a first conductivity type under the gate region being disposed adjacent to active regions of a first conductivity type. The well forming an electrical path between the active regions regardless of any reasonable voltage applied to the integrated circuit structure.
摘要翻译： 用于伪装集成电路结构的技术和结构。 集成电路结构形成为具有第一导电类型的阱，栅极区域邻近第一导电类型的有源区设置。 该阱在有源区域之间形成电路径，而不管施加到集成电路结构的任何合理的电压。
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公开(公告)号：US07008873B2
公开(公告)日：2006-03-07
申请号：US11089415
申请日：2005-03-23
IPC分类号： H01L21/44 , H01L21/00 , H01L21/84 , H01L21/338 , H01L21/4763
CPC分类号： H01L23/573 , H01L27/02 , H01L27/0203 , H01L2924/0002 , H01L2924/00
摘要： Technique and structures for camouflaging an integrated circuit structure. The integrated circuit structure is formed by a plurality of layers of material having controlled outlines and controlled thicknesses. A layer of dielectric material of a controlled thickness is disposed among said plurality of layers to thereby render the integrated circuit structure intentionally inoperable.
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20.发明授权Integrated circuits protected against reverse engineering and method for fabricating the same using vias without metal terminations 失效防止逆向工程的集成电路和使用无金属端接的通孔制造相同工艺的方法公开(公告)号：US06791191B2
公开(公告)日：2004-09-14
申请号：US09768911
申请日：2001-01-24
IPC分类号： H01L2348
CPC分类号： H01L23/573 , H01L23/5226 , H01L27/0203 , H01L2924/0002 , Y10S438/926 , H01L2924/00
摘要： A device adapted to protect integrated circuits from reverse engineering comprising a part looking like a via connecting two metal layers, but in fact attached only to one metal layer and spaced from the other. Having such “trick” via would force a reverse engineer to think there is a connection where there is none. A method for fabricating such device.
摘要翻译： 一种适用于保护集成电路免受反向工程的设备，包括看起来像连接两个金属层的通孔的部分，但实际上仅附接到一个金属层并与另一个间隔开。 通过这样的“诡计”将迫使反向工程师认为没有连接。 一种制造这种装置的方法。
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