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公开(公告)号：US20090170255A1
公开(公告)日：2009-07-02
申请号：US12399628
申请日：2009-03-06
IPC分类号： H01L21/8238
CPC分类号： H01L21/823892 , H01L27/02
摘要： A technique for and structures for camouflaging an integrated circuit structure. The integrated circuit structure is formed having a well of a first conductivity type under the gate region being disposed adjacent to active regions of a first conductivity type. The well forming an electrical path between the active regions regardless of any reasonable voltage applied to the integrated circuit structure.
摘要翻译： 用于伪装集成电路结构的技术和结构。 集成电路结构形成为具有第一导电类型的阱，栅极区域邻近第一导电类型的有源区设置。 该阱在有源区域之间形成电路径，而不管施加到集成电路结构的任何合理的电压。
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2.发明授权Permanently on transistor implemented using a double polysilicon layer CMOS process with buried contact 失效永久性地使用采用双重多晶硅层CMOS工艺的埋入触点实现晶体管公开(公告)号：US06740942B2
公开(公告)日：2004-05-25
申请号：US09882892
申请日：2001-06-15
IPC分类号： H01L2976
CPC分类号： H01L27/0203 , H01L21/76895 , H01L21/823462 , H01L23/576 , H01L27/0883 , H01L29/7834 , H01L2924/0002 , Y10S257/922 , H01L2924/00
摘要： A permanently-ON MOS transistor comprises silicon source and drain regions of a first conductivity type in a silicon well region of a second conductivity type. A silicon contact region of the first conductivity types is buried in the well region, said contact region contacting said source region and said drain region. A first gate insulating layer is selectively placed over the silicon source and drain regions. A second gate insulating layer is selectively placed over the first gate insulating layer and over the silicon contact region. A polysilicon gate region is placed over the second gate insulating layer.
摘要翻译： 永久导通MOS晶体管包括在第二导电类型的硅阱区域中的第一导电类型的硅源极和漏极区域。 所述第一导电类型的硅接触区域埋在所述阱区域中，所述接触区域接触所述源极区域和所述漏极区域。 选择性地将第一栅极绝缘层放置在硅源极和漏极区域上。 第二栅极绝缘层选择性地放置在第一栅极绝缘层上方和硅接触区域上。 多晶硅栅极区域放置在第二栅极绝缘层上。
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公开(公告)号：US07344932B2
公开(公告)日：2008-03-18
申请号：US11208470
申请日：2005-08-18
IPC分类号： H01L21/338
CPC分类号： H01L23/573 , H01L27/02 , H01L2924/0002 , H01L2924/00
摘要： A technique for and structures for camouflaging an integrated circuit structure. A layer of conductive material having a controlled outline is disposed to provide artifact edges of the conductive material that resemble an operable device when in fact the device is not operable.
摘要翻译： 用于伪装集成电路结构的技术和结构。 设置具有受控轮廓的导电材料层，以便当实际上该装置不可操作时，提供类似于可操作装置的导电材料的假象边缘。
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4.发明授权Conductive channel pseudo block process and circuit to inhibit reverse engineering 有权导电通道伪块处理和电路抑制逆向工程公开(公告)号：US07049667B2
公开(公告)日：2006-05-23
申请号：US10635790
申请日：2003-08-05
IPC分类号： H01L29/76
CPC分类号： H01L27/0203 , G06K19/073 , G06K19/07363 , H01L23/573 , H01L2924/0002 , H01L2924/00
摘要： A technique for and structures for camouflaging an integrated circuit structure. The integrated circuit structure is formed by a plurality of layers of material having a controlled outline. A layer of conductive material having a controlled outline is disposed among said plurality of layers to provide artifact edges of the conductive material that resemble one type of transistor (operable vs. non-operable), when in fact another type of transistor was used.
摘要翻译： 用于伪装集成电路结构的技术和结构。 集成电路结构由具有受控轮廓的多层材料形成。 具有受控轮廓的导电材料层设置在所述多个层中，以提供类似于一种类型的晶体管（可操作与不可操作的）的导电材料的伪影边缘，当实际上使用另一种类型的晶体管时。
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5.发明授权Memory with a bit line block and/or a word line block for preventing reverse engineering 失效具有位线块和/或字线块的存储器用于防止逆向工程公开(公告)号：US06940764B2
公开(公告)日：2005-09-06
申请号：US10451673
申请日：2002-03-12
IPC分类号： G11C17/18 , G06F12/14 , G11C7/12 , G11C7/18 , G11C7/24 , G11C16/02 , G11C16/22 , H01L21/8246 , H01L21/8247 , H01L27/02 , H01L27/10 , H01L27/112 , H01L27/115 , G11C7/00
摘要： A method and circuit for blocking unauthorized access to at least one memory cell in a semiconductor memory. The method includes providing a switch and/or a link which assumes an open state when access to the at least one memory cell is to be blocked; and coupling-a data line associated with the at least one memory cell to a constant voltage source in response to the switch or link assuming an open state.
摘要翻译： 一种用于阻止未经授权的访问半导体存储器中的至少一个存储单元的方法和电路。 该方法包括提供在要阻止对至少一个存储器单元的访问时呈现打开状态的开关和/或链接; 以及响应于所述开关或链路假定为打开状态，将与所述至少一个存储器单元相关联的数据线耦合到恒定电压源。
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6.发明授权Programmable connector/isolator and double polysilicon layer CMOS process with buried contact using the same 失效可编程连接器/隔离器和双层多晶硅层CMOS工艺与埋地接触使用相同公开(公告)号：US06893916B2
公开(公告)日：2005-05-17
申请号：US10619981
申请日：2003-07-14
IPC分类号： H01L21/768 , H01L27/02 , H01L21/8242 , H01L21/336 , H01L21/00
CPC分类号： H01L27/02 , H01L21/76895 , H01L23/573 , H01L27/0203
摘要： An integrated circuit structure for MOS-type devices including a silicon substrate of a first conductivity type; a first gate insulating regions selectively placed over the silicon substrate of the first conductivity tape; a first polycrystalline silicon layer selectively placed over the silicon substrate of the first conductivity type; a second gate insulating regions selectively placed over the first gate insulating regions and the first polycrystalline silicon layer; a second polycrystalline silicon layer selectively placed over the second gate insulating regions; first buried silicon regions of a second conductivity type, buried within the silicon substrate of the first conductivity type, placed under the first polycrystalline silicon layer and in contact therewith; and second buried silicon regions of the second conductivity type, buried within the silicon substrate of the first conductivity type, placed under the second gate insulating regions, under the second polycrystalline silicon layer and insulated therefrom.
摘要翻译： 一种用于包括第一导电类型的硅衬底的MOS器件的集成电路结构; 选择性地放置在第一导电带的硅衬底上的第一栅绝缘区; 选择性地放置在第一导电类型的硅衬底上的第一多晶硅层; 选择性地放置在所述第一栅极绝缘区域和所述第一多晶硅层上的第二栅极绝缘区域; 选择性地放置在所述第二栅极绝缘区域上的第二多晶硅层; 埋在第一导电类型的硅衬底内的第二导电类型的第一掩埋硅区域放置在第一多晶硅层下方并与其接触; 以及第二导电类型的第二掩埋硅区域，埋在第一导电类型的硅衬底内，放置在第二栅极绝缘区域的下面，在第二多晶硅层下方并与其绝缘。
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公开(公告)号：US06294816B1
公开(公告)日：2001-09-25
申请号：US09087748
申请日：1998-05-29
IPC分类号： H01L2976
CPC分类号： H01L23/573 , G11C7/24 , H01L27/02 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit is protected from reverse engineering by connecting doped circuit elements of like conductivity with a doped implant in the substrate, rather than with a metallized interconnect. The doped circuit elements and their corresponding implant interconnections can be formed in a common fabrication step with common implant masks, such that they have an integral structure with similar dopant concentrations. The metallization above the substrate surface can be designed to provide further masking of the interconnects, and microbridges can be added to span strips of transistor gate material in the interconnect path.
摘要翻译： 通过将类似导电性的掺杂电路元件与衬底中的掺杂注入相连而不是金属化互连来保护集成电路免于逆向工程。 掺杂电路元件及其对应的注入互连可以在具有公共注入掩模的公共制造步骤中形成，使得它们具有类似掺杂剂浓度的整体结构。 衬底表面之上的金属化可被设计成提供互连的进一步屏蔽，并且微桥可以被添加到在互连路径中跨越晶体管栅极材料的条带。
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8.发明授权公开(公告)号：US07541266B2
公开(公告)日：2009-06-02
申请号：US11710114
申请日：2007-02-22
IPC分类号： H01L21/425
CPC分类号： H01L21/823814 , H01L23/573 , H01L27/02 , H01L27/092
摘要： A technique for and structures for camouflaging an integrated circuit structure. The technique includes the use of a light density dopant (LDD) region of opposite type from the active regions resulting in a transistor that is always off when standard voltages are applied to the device.
摘要翻译： 用于伪装集成电路结构的技术和结构。 该技术包括使用与有源区域相反类型的光密度掺杂剂（LDD）区域，导致当标准电压施加到器件时总是关闭的晶体管。
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9.发明授权公开(公告)号：US07217977B2
公开(公告)日：2007-05-15
申请号：US10828022
申请日：2004-04-19
IPC分类号： H01L31/062 , H01L31/113
CPC分类号： H01L21/823814 , H01L23/573 , H01L27/02 , H01L27/092
摘要： A technique for and structures for camouflaging an integrated circuit structure. The technique includes the use of a light density dopant (LDD) region of opposite type from the active regions resulting in a transistor that is always off when standard voltages are applied to the device.
摘要翻译： 用于伪装集成电路结构的技术和结构。 该技术包括使用与有源区域相反类型的光密度掺杂剂（LDD）区域，导致当标准电压施加到器件时总是关闭的晶体管。
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10.发明授权Implanted hidden interconnections in a semiconductor device for preventing reverse engineering 有权在半导体器件中隐藏的互连用于防止逆向工程公开(公告)号：US07166515B2
公开(公告)日：2007-01-23
申请号：US10132523
申请日：2002-04-24
IPC分类号： H01L21/336
CPC分类号： H01L27/02 , H01L21/743
摘要： A camouflaged interconnection for interconnecting two spaced-apart regions of a common conductivity type in an integrated circuit or device and a method of forming same. The camouflaged interconnection comprises a first region forming a conducting channel between the two spaced-apart regions, the conducting channel being of the same common conductivity type and bridging a region between the two spaced-apart regions, and a second region of opposite conductivity to type, the second region being disposed between the two spaced-apart regions of common conductivity type and over lying the conducting channel to camouflage the conducting channel from reverse engineering.
摘要翻译： 用于在集成电路或器件中互连公共导电类型的两个间隔开的区域的伪装互连和其形成方法。 伪装的互连包括在两个间隔开的区域之间形成导电通道的第一区域，导电沟道具有相同的共同导电类型并桥接两个间隔开的区域之间的区域，以及与类型相反的导电性的第二区域 所述第二区域设置在所述公共导电类型的两个间隔开的区域之间，并且位于所述导电通道上以伪装所述导电通道以进行逆向工程。
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