公开(公告)号：US5712856A

公开(公告)日：1998-01-27

申请号：US749880

申请日：1996-11-15

申请人： Damon W. Finney ,  Michael James Rayfield

发明人： Damon W. Finney ,  Michael James Rayfield

IPC分类号： G06F11/22 ,  G06F13/00 ,  H04L12/26 ,  H04L29/06 ,  H04L29/14 ,  H04M3/22 ,  G01R31/28 ,  G06F11/00

CPC分类号： H04L43/50 ,  H04L12/2697 ,  H04L29/06 ,  H04L69/03

摘要： A test link protocol which continuously monitors each link in a network to ensure that the link is correctly transmitting data. Each switch, or torus has at least one of two functional components: Send Test and Receive Test. The Send Test component monitors control codes at a torus link output. The Receive Test component monitors control codes at a torus link input. After a predetermined interval, the Send Test component makes a request to send a test.sub.-- link control code. The torus sends the test.sub.-- link code to the neighboring torus, where it is removed from the data stream and sent to that torus' Receive Test. The Receive Test then generates a response message and makes a request to send that message back to the originating torus. After receiving the message, the Send Test analyzes the message to determine whether the network link is working correctly. An error is also declared if the Send Test does not receive a reply within a predetermined interval.

摘要翻译： 一种连续监视网络中每个链路以确保链路正确传输数据的测试链路协议。 每个开关或环面至少有两个功能组件之一：发送测试和接收测试。 发送测试组件监视环面链路输出端的控制代码。 接收测试组件监视环面连接输入端的控制代码。 在预定的时间间隔之后，发送测试组件请求发送测试链接控制代码。 环形天线将测试链接代码发送到相邻的环面，从数据流中删除并发送到该环面的“接收测试”。 接收测试然后生成一个响应消息，并发出请求将该消息发送回原始环面。 收到消息后，发送测试分析消息以确定网络链路是否正常工作。 如果发送测试没有在预定的时间间隔内收到回复，也会声明错误。

公开(公告)号：US5687393A

公开(公告)日：1997-11-11

申请号：US480010

申请日：1995-06-07

申请人： Lawrence Marcel Brown ,  Damon W. Finney ,  George Bohoslaw Marenin ,  Adalberto Guillermo Yanes

发明人： Lawrence Marcel Brown ,  Damon W. Finney ,  George Bohoslaw Marenin ,  Adalberto Guillermo Yanes

IPC分类号： G06F13/42 ,  G06F13/16 ,  G06F13/20 ,  G06F13/36

CPC分类号： G06F13/161 ,  G06F13/1615

摘要： A data processing system includes one or more processors connected to a common bus, one or more I/O controllers connected to the common bus and to one or more storage subsystems and one or more storage subsystems for storing data for use in the data processing system. One or more master controllers are included in each I/O controller for communicating with a memory controller referred to as a slave which controls data flow to and from a memory subsystem. The data bus between the I/O masters and the memory controller is a multi-drop operating synchronously on a two-by-two byte parallel interface.

摘要翻译： 数据处理系统包括连接到公共总线的一个或多个处理器，连接到公共总线的一个或多个I / O控制器和一个或多个存储子系统以及用于存储用于数据处理系统的数据的一个或多个存储子系统 。 一个或多个主控制器被包括在每个I / O控制器中，用于与被称为从属的存储器控​​制器进行通信，所述存储器控制器控制到存储器子系统和从存储器子系统的数据流。 I / O主机和存储器控制器之间的数据总线是在两位二字节并行接口上同步进行多点操作。

公开(公告)号：US5570356A

公开(公告)日：1996-10-29

申请号：US486541

申请日：1995-06-07

申请人： Damon W. Finney ,  Michael O. Jenkins ,  Michael J. Rayfield

发明人： Damon W. Finney ,  Michael O. Jenkins ,  Michael J. Rayfield

IPC分类号： H04Q11/04 ,  H04J3/06

CPC分类号： H04Q11/04

摘要： A data communication system includes a phase splitting circuit to split a high speed parallel data word into a number of individual parallel data bytes, a byte multiplexor for each of the phases of a phase splitting circuit, encoding and serialization circuits for converting each byte such as an 8-bit byte to an encoded form suitable for serial transmission such as by employing the Widmer et al. 8-bit/10-bit code, transmitting each encoded byte across one of a number of serial transmission links to a receiving device where the data is deserialized and decoded to recover the original byte which is then synchronized by a byte synchronization circuit. The byte synchronization circuits are then coupled to a word synchronization circuit where the original high bandwidth data word is recovered and transmitted on an internal high speed parallel bus within the receiving device.

摘要翻译： 数据通信系统包括：将高速并行数据字分割为若干个并行数据字节的相位分离电路，分相电路的每个相位的字节多路复用器，用于转换每个字节的编码和串行化电路， 一个8位字节到适合于串行传输的编码形式，例如通过使用Widmer等人 8位/ 10位代码，将多个串行传输链路之一的每个编码字节传送到数据被反序列化和解码的接收设备，以恢复原始字节，然后由字节同步电路同步。 字节同步电路然后被耦合到字同步电路，其中原始高带宽数据字被恢复并在接收设备内的内部高速并行总线上传输。

公开(公告)号：US5857213A

公开(公告)日：1999-01-05

申请号：US761639

申请日：1996-12-06

申请人： Michael T. Benhase ,  James Thomas Brady ,  Damon W. Finney ,  Michael Howard Hartung ,  Michael Anthony Ko ,  Donald J. Lang ,  Jaishankar Moothedath Menon

发明人： Michael T. Benhase ,  James Thomas Brady ,  Damon W. Finney ,  Michael Howard Hartung ,  Michael Anthony Ko ,  Donald J. Lang ,  Jaishankar Moothedath Menon

IPC分类号： G06F3/06 ,  G06F12/02

CPC分类号： G06F3/0608 ,  G06F3/064 ,  G06F3/0689

摘要： A method enables a host processor, which employs variable length (VL) records, to communicate with disk storage which employs fixed length (FL) sectors for storage of the VL records. The method comprises the steps of: a) deriving a first control data structure for an update VL record, the first control data structure including information describing segments of the update VL record; b) determining a disk track that includes a FL sector wherein am old VL record commences that corresponds to the update VL record; c) reading each FL sector in the disk track and creating a control data structure which includes information describing each VL record stored in the disk track; d) substituting in a control data structure for the old VL record that corresponds to the update VL record, information regarding update data from the first control data structure; e) recording in the disk track, data indicated by each control data structure determined in steps c) and d); and f) if the old VL record ends at other than a sector break of a FL sector, reblocking VL records into FL sectors which are recorded thereafter on the disk track. The invention also enables a read action to be accomplished in one rotation of a disk even though it commences at a FL sector that is not at the beginning of a VL record to be accessed.

摘要翻译： 一种方法使得采用可变长度（VL）记录的主机处理器与采用固定长度（FL）扇区的磁盘存储器通信以存储VL记录。 该方法包括以下步骤：a）导出更新VL记录的第一控制数据结构，所述第一控制数据结构包括描述更新VL记录段的信息; b）确定包括FL扇区的磁盘轨道，其中旧的VL记录开始对应于更新VL记录; c）读取磁盘轨道中的每个FL扇区并创建包括描述存储在磁盘轨道中的每个VL记录的信息的控制数据结构; d）用对应于更新VL记录的旧VL记录的控制数据结构替换关于来自第一控制数据结构的更新数据的信息; e）在盘轨道中记录由步骤c）和d）中确定的每个控制数据结构指示的数据; 以及f）如果旧的VL记录在FL扇区的扇区断点之外结束，则将VL记录重新锁定到其后记录在磁盘轨道上的FL扇区中。 本发明还使得能够在盘的一次旋转中实现读取动作，即使其在不在要访问的VL记录的开始处的FL扇区处开始。

公开(公告)号：US5603044A

公开(公告)日：1997-02-11

申请号：US385761

申请日：1995-02-08

申请人： Narasimhareddy L. Annapareddy ,  Damon W. Finney ,  Michael O. Jenkins ,  Larry B. Kessler ,  Donald J. Lang ,  Song C. Liang ,  David N. Mora ,  David A. Plomgren ,  Peter P. Urbisci ,  Andrew D. Walls

发明人： Narasimhareddy L. Annapareddy ,  Damon W. Finney ,  Michael O. Jenkins ,  Larry B. Kessler ,  Donald J. Lang ,  Song C. Liang ,  David N. Mora ,  David A. Plomgren ,  Peter P. Urbisci ,  Andrew D. Walls

IPC分类号： G06F15/173 ,  G06F1/18 ,  G06F13/40 ,  G06F9/02

CPC分类号： G06F13/409

摘要： An interconnection network comprises a pair of backplanes for receiving X pluggable node cards. The pair of backplanes include X backplane connector groups, each backplane connector group adapted to receive mating connectors from a pluggable node card. Each backplane connector group includes X/2 connectors. A first backplane includes first permanent wiring which interconnects a first subset of pairs of connectors between backplane connector groups. A second backplane includes second permanent wiring which interconnects a second subset of pairs of connectors between backplane connector groups. The first permanent wiring and second permanent wiring connect complementary subsets' of pairs of the connectors. A plurality of node cards, each including a card connector group, pluggably mate with the backplane connector groups. Each node card further includes a frontal connector that is adapted to receive a cable interconnection. Each node card includes a processor and a switch module which simultaneously connects the processor to at least plural connectors of a backplane connector group.

摘要翻译： 互连网络包括用于接收X个可插拔节点卡的一对背板。 该对背板包括X个背板连接器组，每个背板连接器组适于从可插拔节点卡接收配对连接器。 每个背板连接器组包括X / 2连接器。 第一背板包括将背板连接器组之间的第一对连接器对互连的第一永久布线。 第二背板包括第二永久布线，其将背板连接器组之间的第二对连接器对互连。 第一个永久布线和第二个永久布线连接了连接器对的互补子集。 多个节点卡，各自包括卡连接器组，可插拔地与背板连接器组配合。 每个节点卡还包括适于接收电缆互连的正面连接器。 每个节点卡包括处理器和开关模块，其将处理器同时连接到背板连接器组的至少多个连接器。

公开(公告)号：US6101194A

公开(公告)日：2000-08-08

申请号：US871165

申请日：1997-06-09

申请人： Narasimha Lakshmi Annapareddy ,  James Thomas Brady ,  Damon W. Finney ,  Michael Howard Hartung ,  Michael Anthony Ko ,  Jai M. Menon ,  David Ronald Nowlen

发明人： Narasimha Lakshmi Annapareddy ,  James Thomas Brady ,  Damon W. Finney ,  Michael Howard Hartung ,  Michael Anthony Ko ,  Jai M. Menon ,  David Ronald Nowlen

IPC分类号： H04J3/02 ,  H04L29/06 ,  H04L29/08

CPC分类号： H04L29/06 ,  H04L29/08

摘要： Conflicts are resolved between competing nodes in a multi-node communications network. After a first node in the network requests an initiation of communications with a target node, the requesting node may simply initiate the requested communications with the target node if the target node is not busy. If the first node determines that the target node is busy, it proceeds to resolve the conflict. Namely, the first node repeats the process of waiting for a first delay then requesting initiation of communications with the target node. After each unsuccessful attempt, the first delay is successively increased. As an example, the delay may be increased exponentially, with a controlled randomness added. After a or more queued messages to other nodes. Following this, the first node performs another sequence to initiate communications with the target node, successively increasing the delay between unsuccessful attempts, as before. After a predetermined number of unsuccessful passes through the foregoing routine, the first node proceeds to take appropriate action, such as initiating an error recovery routine, sending the message via different hardware components, or issuing an error message.

摘要翻译： 冲突在多节点通信网络中的竞争节点之间解决。 在网络中的第一节点请求启动与目标节点的通信之后，如果目标节点不忙，请求节点可以简单地发起与目标节点的所请求的通信。 如果第一个节点确定目标节点正在忙，则会继续解决冲突。 也就是说，第一节点重复等待第一延迟的处理，然后请求发起与目标节点的通信。 在每次不成功的尝试后，第一个延迟连续增加。 作为示例，延迟可以以指数方式增加，并且增加受控的随机性。 将一个或多个排队的消息发送到其他节点。 此后，第一个节点执行另一个序列以启动与目标节点的通信，如以前一样，连续增加不成功尝试之间的延迟。 在通过上述例程的预定数量的不成功通过之后，第一节点继续采取适当的动作，例如启动错误恢复例程，经由不同硬件组件发送消息或发出错误消息。

公开(公告)号：US5860088A

公开(公告)日：1999-01-12

申请号：US761719

申请日：1996-12-06

申请人： Michael T. Benhase ,  James Thomas Brady ,  Damon W. Finney ,  Michael Howard Hartung ,  Michael Anthony Ko ,  Donald J. Lang ,  Jaishankar Moothedath Menon

发明人： Michael T. Benhase ,  James Thomas Brady ,  Damon W. Finney ,  Michael Howard Hartung ,  Michael Anthony Ko ,  Donald J. Lang ,  Jaishankar Moothedath Menon

IPC分类号： G06F3/06 ,  G06F12/02

CPC分类号： G06F3/0608 ,  G06F3/064 ,  G06F3/0661 ,  G06F3/0689

摘要： A method enables a host processor, which employs variable length (VL) records, to transparently communicate with disk storage which employs fixed length (FL) sectors for storage of the VL records. The method comprises the steps of: a) deriving a first control data structure for an update VL record, the first control data structure including information describing segments of the update VL record; b) determining an FL sector wherein an old VL record commences that corresponds to the update VL record; c) if the old VL record commences at other than a sector break of the FL sector, deriving a second control data structure for a portion of a prior VL record that immediately precedes the old VL record and a third control data structure for the old VL record; d) substituting in the third control data structure, information regarding update segments of the update VL record from the first control data structure; and recording in the FL sector determined in c), data indicated by the second control data structure and at least a portion of the update VL record, through use of the third control structure as altered in d).

摘要翻译： 一种方法使得采用可变长度（VL）记录的主机处理器与采用固定长度（FL）扇区的磁盘存储器透明地通信以存储VL记录。 该方法包括以下步骤：a）导出更新VL记录的第一控制数据结构，所述第一控制数据结构包括描述更新VL记录段的信息; b）确定FL扇区，其中旧VL记录开始对应于更新VL记录; c）如果旧的VL记录在FL扇区的扇区之外开始，则导出紧邻旧VL记录之前的先前VL记录的一部分的第二控制数据结构，以及旧VL的第三控制数据结构 记录; d）在第三控制数据结构中替换关于来自第一控制数据结构的更新VL记录的更新段的信息; 并且通过使用在d）中改变的第三控制结构，在c）确定的FL扇区中记录由第二控制数据结构指示的数据和更新VL记录的至少一部分。

公开(公告)号：US5845072A

公开(公告)日：1998-12-01

申请号：US850284

申请日：1997-05-05

申请人： Damon W. Finney ,  Wen-Jei Ho ,  Mark C. Johnson ,  Donald J. Lang

发明人： Damon W. Finney ,  Wen-Jei Ho ,  Mark C. Johnson ,  Donald J. Lang

IPC分类号： G06F17/50 ,  G06F13/00

CPC分类号： G06F17/5045

摘要： A common macro interface between chips that have design features in common and communicate with each other. The common macro interface (CMI) uses VHDL (VHSIC Hardware Description Language) which is the industry standard hardware design language. A common protocol is provided to resolve communication problems and comprises four signals: request; acknowledge request; data acknowledge, and read/write. A freeway system within the interfaces facilitates parallel and pipelining processes and an arbiter (also called a scheduler) is placed in front of every slave resource to control the traffic independently and to avoid traffic collisions from locking the freeway. The freeway is unique for each integrated circuit. Accordingly, macros may be moved from chip to chip without requiring complete system modifications and the effort involved in designing macros common to several chips may be shared.

摘要翻译： 具有共同设计特征并相互通信的芯片之间的通用宏接口。 通用宏接口（CMI）使用行业标准硬件设计语言VHDL（VHSIC硬件描述语言）。 提供通用协议来解决通信问题，包括四个信号：请求; 确认要求; 数据确认和读/写。 接口内的高速公路系统有助于并行和流水线处理，仲裁器（也称为调度器）被放置在每个从属资源的前面，以独立控制流量，避免交通碰撞锁定高速公路。 高速公路对于每个集成电路是独一无二的。 因此，宏可以从芯片移动到芯片，而不需要完整的系统修改，并且可以共享用于设计几个芯片通用的宏的努力。

公开(公告)号：US5717862A

公开(公告)日：1998-02-10

申请号：US429702

申请日：1995-04-27

申请人： Narasimhareddy L. Annapareddy ,  James Thomas Brady ,  Damon W. Finney ,  Richard F. Freitas ,  Michael Anthony Ko ,  Michael James Rayfield

发明人： Narasimhareddy L. Annapareddy ,  James Thomas Brady ,  Damon W. Finney ,  Richard F. Freitas ,  Michael Anthony Ko ,  Michael James Rayfield

IPC分类号： H04L12/56 ,  G06F13/00

CPC分类号： H04L47/10

摘要： A multi-nodal data processing system includes a plurality of processing nodes, each node connected to plural other nodes by bidirectional data links. Each node comprises receivers for receiving messages on bidirectional data links and transmitters for transmitting messages on bidirectional data links. Each node records child nodes to which a message was transmitted and is further adapted to transmit a lock-up message received from a child node to a parent node, the lock-up message indicating a successful establishment of a message signal path to a destination node. Each node further is adapted to transmit a link cancel signal to another node to close the link in the event of an unsuccessful message transfer attempt over the link. Each node inhibits transmission of a lock-up signal to a parent node until link cancel signals have been received from all child nodes (other than a node from which a lock-up signal was received). A source node (where a message originates) continues transmission of its message, even before a lock-up signal has been received. The destination node which originates the lock-up message terminates a bidirectional data link by an end-of-session signal when it has received an entire message.

摘要翻译： 多节点数据处理系统包括多个处理节点，每个节点通过双向数据链路连接到多个其他节点。 每个节点包括用于在双向数据链路上接收消息的接收机和用于在双向数据链路上发送消息的发射机。 每个节点记录发送消息的子节点，并且进一步适于将从子节点接收的锁定消息发送到父节点，锁定消息指示成功建立到目的地节点的消息信号路径 。 每个节点进一步适于在另一节点上发送链路取消信号以在通过链路的不成功的消息传送尝试的情况下关闭链路。 每个节点禁止向父节点发送锁定信号，直到从所有子节点（除了接收到锁定信号的节点）接收到链路消除信号为止。 即使在接收到锁定信号之前，源节点（消息始发地）也继续发送其消息。 当接收到整个消息时，发起锁定消息的目的地节点通过会话结束信号终止双向数据链路。