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公开(公告)号：US20120168832A1
公开(公告)日：2012-07-05
申请号：US13246175
申请日：2011-09-27
IPC分类号： H01L29/78
CPC分类号： H01L29/0847 , H01L29/665 , H01L29/66628 , H01L29/66636 , H01L29/66659 , H01L29/78 , H01L29/7834 , H01L29/7835
摘要： Disclosed are embodiments of an asymmetric field effect transistor structure and a method of forming the structure in which both series resistance in the source region (Rs) and gate to drain capacitance (Cgd) are reduced in order to provide optimal performance (i.e., to provide improved drive current with minimal circuit delay). Specifically, different heights of the source and drain regions and/or different distances between the source and drain regions and the gate are tailored to minimize series resistance in the source region (i.e., in order to ensure that series resistance is less than a predetermined resistance value) and in order to simultaneously to minimize gate to drain capacitance (i.e., in order to simultaneously ensure that gate to drain capacitance is less than a predetermined capacitance value).
摘要翻译： 公开了非对称场效应晶体管结构的实施例和形成其中源极区（Rs）和栅极 - 漏极电容（Cgd）中的串联电阻都被降低以便提供最佳性能（即提供 改进的驱动电流，电路延迟最小）。 具体地说，源极和漏极区域的不同高度和/或源极和漏极区域与栅极之间的不同距离被调整以最小化源极区域中的串联电阻（即，为了确保串联电阻小于预定电阻 值），并且为了同时使栅极 - 漏极电容最小化（即，为了同时确保栅极到漏极电容小于预定的电容值）。
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公开(公告)号：US07843016B2
公开(公告)日：2010-11-30
申请号：US11869145
申请日：2007-10-09
IPC分类号： H01L29/78
CPC分类号： H01L29/0847 , H01L29/665 , H01L29/66628 , H01L29/66636 , H01L29/66659 , H01L29/78 , H01L29/7834 , H01L29/7835
摘要： Disclosed are embodiments for a design structure of an asymmetric field effect transistor structure and a method of forming the structure in which both series resistance in the source region (Rs) and gate to drain capacitance (Cgd) are reduced in order to provide optimal performance (i.e., to provide improved drive current with minimal circuit delay). Specifically, different heights of the source and drain regions and/or different distances between the source and drain regions and the gate are tailored to minimize series resistance in the source region (i.e., in order to ensure that series resistance is less than a predetermined resistance value) and in order to simultaneously to minimize gate to drain capacitance (i.e., in order to simultaneously ensure that gate to drain capacitance is less than a predetermined capacitance value).
摘要翻译： 公开了用于非对称场效应晶体管结构的设计结构的实施例以及形成其中源极区（Rs）和栅极 - 漏极电容（Cgd）中的串联电阻都被降低以便提供最佳性能（ 即，以最小的电路延迟来提供改进的驱动电流）。 具体地说，源极和漏极区域的不同高度和/或源极和漏极区域与栅极之间的不同距离被调整以最小化源极区域中的串联电阻（即，为了确保串联电阻小于预定电阻 值），并且为了同时使栅极 - 漏极电容最小化（即，为了同时确保栅极到漏极电容小于预定的电容值）。
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公开(公告)号：US20090189223A1
公开(公告)日：2009-07-30
申请号：US12022292
申请日：2008-01-30
IPC分类号： H01L21/8238 , H01L27/092
CPC分类号： H01L21/823842 , H01L21/76895 , H01L21/823871
摘要： Complementary metal gate dense interconnects and methods of manufacturing the interconnects is provided. The method comprises forming a first metal gate on a wafer and second metal gate on the wafer. A conductive interconnect material is deposited in a space formed between the first metal gate and the second metal gate to provide an electrical connection between the first metal gate and the second metal gate.
摘要翻译： 提供互补金属栅极致密互连和制造互连的方法。 该方法包括在晶片上形成第一金属栅极和在晶片上形成第二金属栅极。 导电互连材料沉积在形成在第一金属栅极和第二金属栅极之间的空间中，以在第一金属栅极和第二金属栅极之间提供电连接。
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14.发明授权Structure including transistor having gate and body in direct self-aligned contact 有权结构包括具有直接自对准接触的门和体的晶体管公开(公告)号：US07937675B2
公开(公告)日：2011-05-03
申请号：US11935612
申请日：2007-11-06
CPC分类号： H01L29/78615
摘要： A design structure including a transistor having a directly contacting gate and body is disclosed. In one embodiment, the transistor includes a gate; a body; and a dielectric layer extending over the body to insulate the gate from the body along an entire surface of the body except along a portion of at least a sidewall of the body, wherein the gate is in direct contact with the body at the portion.
摘要翻译： 公开了一种包括具有直接接触的栅极和主体的晶体管的设计结构。 在一个实施例中，晶体管包括栅极; 身体; 以及电介质层，其延伸到所述主体上，以沿着所述主体的至少一个侧壁的一部分沿着所述主体的整个表面使所述门与所述主体绝缘，其中所述门在所述部分处与所述主体直接接触。
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15.发明授权公开(公告)号：US07910418B2
公开(公告)日：2011-03-22
申请号：US12022292
申请日：2008-01-30
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L21/823842 , H01L21/76895 , H01L21/823871
摘要： Complementary metal gate dense interconnects and methods of manufacturing the interconnects is provided. The method comprises forming a first metal gate on a wafer and second metal gate on the wafer. A conductive interconnect material is deposited in a space formed between the first metal gate and the second metal gate to provide an electrical connection between the first metal gate and the second metal gate.
摘要翻译： 提供互补金属栅极致密互连和制造互连的方法。 该方法包括在晶片上形成第一金属栅极和在晶片上形成第二金属栅极。 导电互连材料沉积在形成在第一金属栅极和第二金属栅极之间的空间中，以在第一金属栅极和第二金属栅极之间提供电连接。
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16.发明授权公开(公告)号：US07816738B2
公开(公告)日：2010-10-19
申请号：US11164651
申请日：2005-11-30
申请人： Brent A. Anderson , Andres Bryant , William F. Clark, Jr. , Jeffrey P. Gambino , Shih-Fen Huang , Edward J. Nowak , Anthony K. Stamper
发明人： Brent A. Anderson , Andres Bryant , William F. Clark, Jr. , Jeffrey P. Gambino , Shih-Fen Huang , Edward J. Nowak , Anthony K. Stamper
IPC分类号： H01L27/088
CPC分类号： H01L21/823412 , H01L21/823418 , H01L29/6653 , H01L29/66545 , H01L29/78
摘要： In order to reduce power dissipation requirements, obtain full potential transistor performance and avoid power dissipation limitations on transistor performance in high density integrated circuits, transistors are operated in a sub-threshold (sub-Vth) or a near sub-Vth voltage regime (generally about 0.2 volts rather than a super-Vth regime of about 1.2 volts or higher) and optimized for such operation, particularly through simplification of the transistor structure, since intrinsic channel resistance is dominant in sub-Vth operating voltage regimes. Such simplifications include an underlap or recess of the source and drain regions from the gate which avoids overlap capacitance to partially recover loss of switching speed otherwise caused by low voltage operation, an ultra-thin gate structure having a thickness of 500 Å or less which also simplifies forming connections to the transistor and an avoidance of silicidation or alloy formation in the source, drain and/or gate of transistors.
摘要翻译： 为了降低功耗要求，获得全电位晶体管性能，并避免在高密度集成电路中对晶体管性能的功耗限制，晶体管工作在亚阈值（sub-Vth）或接近sub-Vth电压方式 约0.2伏，而不是约1.2伏特或更高的超电压状态），并且为了这种操作而进行了优化，特别是通过简化晶体管结构，因为在Vth的工作电压方案中固有的沟道电阻是主要的。 这种简化包括来自栅极的源极和漏极区域的欠叠或凹陷，其避免重叠电容以部分恢复由低电压操作引起的切换速度的损失，厚度为或等于或小于500埃的超薄栅极结构 简化了与晶体管的形成连接，避免了晶体管的源极，漏极和/或栅极中的硅化或合金形成。
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公开(公告)号：US07494850B2
公开(公告)日：2009-02-24
申请号：US11276135
申请日：2006-02-15
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/11
摘要： Disclosed are embodiments of a structure that comprises a first device, having multiple FETs, and a second device, having at least one FET. Sections of a first portion of a semiconductor layer below the first device are doped and contacted to form back gates. A second portion of the semiconductor layer below the second device remains un-doped and un-contacted and, thus, functions as an insulator. Despite the performance degradation of the first device due to back gate capacitance, the back gates result in a net gain for devices such as, SRAM cells, which require precise Vt control. Contrarily, despite marginal Vt control in the second device due to the absence of back gates, the lack of capacitance loading and the added insulation result in a net gain for high performance devices such as, logic circuits.
摘要翻译： 公开了包括具有多个FET的第一器件和具有至少一个FET的第二器件的结构的实施例。 第一器件下方的半导体层的第一部分的部分被掺杂并接触以形成后栅极。 第二器件下方的半导体层的第二部分保持未掺杂和未接触，并因此用作绝缘体。 尽管由于背栅电容而导致第一器件的性能下降，但是后栅导致需要精确Vt控制的诸如SRAM单元的器件的净增益。 相反，尽管由于不存在后门而导致第二器件中的边缘Vt控制，但由于缺少电容负载和增加的绝缘，导致高性能器件（如逻辑电路）的净增益。
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公开(公告)号：US08557624B2
公开(公告)日：2013-10-15
申请号：US13005650
申请日：2011-01-13
申请人： Brent A. Anderson , Andres Bryant , William F. Clark, Jr. , John Joseph Ellis-Monaghan , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , William F. Clark, Jr. , John Joseph Ellis-Monaghan , Edward J. Nowak
IPC分类号： H01L21/00 , H01L31/113 , G06F17/50 , H01L31/18
CPC分类号： H01L27/14614 , H01L27/14689
摘要： Pixel sensor cells, methods of fabricating pixel sensor cells, and design structures for a pixel sensor cell. A transistor in the pixel sensor cell has a gate structure that includes a gate dielectric with a thick region and a thin region. A gate electrode of the gate structure is formed on the thick region of the gate dielectric and the thin region of the gate dielectric. The thick region of the gate dielectric and the thin region of the gate dielectric provide the transistor with an asymmetric threshold voltage.
摘要翻译： 像素传感器单元，制造像素传感器单元的方法以及像素传感器单元的设计结构。 像素传感器单元中的晶体管具有包括具有厚区域和薄区域的栅极电介质的栅极结构。 栅极结构的栅电极形成在栅极电介质的厚区域和栅极电介质的薄区域上。 栅极电介质的厚区域和栅极电介质的薄区为晶体管提供非对称阈值电压。
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公开(公告)号：US08299505B2
公开(公告)日：2012-10-30
申请号：US13029670
申请日：2011-02-17
申请人： Brent A. Anderson , Andres Bryant , William F. Clark, Jr. , John Joseph Ellis-Monaghan , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , William F. Clark, Jr. , John Joseph Ellis-Monaghan , Edward J. Nowak
IPC分类号： H01L27/148
CPC分类号： H01L27/14614
摘要： Pixel sensor cells, methods of fabricating pixel sensor cells, and design structures for a pixel sensor cell. The pixel sensor cell has a gate structure that includes a gate dielectric and a gate electrode on the gate dielectric. The gate electrode includes a layer with first and second sections that have a juxtaposed relationship on the gate dielectric. The second section of the gate electrode is comprised of a conductor, such as doped polysilicon or a metal. The first section of the gate electrode is comprised of a metal having a higher work function than the conductor comprising the second section so that the gate structure has an asymmetric threshold voltage.
摘要翻译： 像素传感器单元，制造像素传感器单元的方法以及像素传感器单元的设计结构。 像素传感器单元具有在栅极电介质上包括栅极电介质和栅电极的栅极结构。 栅极电极包括具有在栅极电介质上具有并置关系的第一和第二部分的层。 栅电极的第二部分由诸如掺杂多晶硅或金属的导体组成。 栅电极的第一部分由具有比包括第二部分的导体更高的功函的金属组成，使得栅极结构具有非对称阈值电压。
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公开(公告)号：US08288806B2
公开(公告)日：2012-10-16
申请号：US13246175
申请日：2011-09-27
IPC分类号： H01L29/78
CPC分类号： H01L29/0847 , H01L29/665 , H01L29/66628 , H01L29/66636 , H01L29/66659 , H01L29/78 , H01L29/7834 , H01L29/7835
摘要： Disclosed are embodiments of an asymmetric field effect transistor structure and a method of forming the structure in which both series resistance in the source region (Rs) and gate to drain capacitance (Cgd) are reduced in order to provide optimal performance (i.e., to provide improved drive current with minimal circuit delay). Specifically, different heights of the source and drain regions and/or different distances between the source and drain regions and the gate are tailored to minimize series resistance in the source region (i.e., in order to ensure that series resistance is less than a predetermined resistance value) and in order to simultaneously to minimize gate to drain capacitance (i.e., in order to simultaneously ensure that gate to drain capacitance is less than a predetermined capacitance value).
摘要翻译： 公开了非对称场效应晶体管结构的实施例和形成其中源极区（Rs）和栅极 - 漏极电容（Cgd）中的串联电阻都被降低以便提供最佳性能（即提供 改进的驱动电流，电路延迟最小）。 具体地说，源极和漏极区域的不同高度和/或源极和漏极区域与栅极之间的不同距离被调整以最小化源极区域中的串联电阻（即，为了确保串联电阻小于预定电阻 值），并且为了同时使栅极 - 漏极电容最小化（即，为了同时确保栅极到漏极电容小于预定的电容值）。
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