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    Low-cost FEOL for ultra-low power, near sub-vth device structures
    1.
    发明授权
    Low-cost FEOL for ultra-low power, near sub-vth device structures 有权
    低成本的FEOL用于超低功耗，靠近次级装置结构

    公开(公告)号：US07816738B2

    公开(公告)日：2010-10-19

    申请号：US11164651

    申请日：2005-11-30

    申请人： Brent A. Anderson ,  Andres Bryant ,  William F. Clark, Jr. ,  Jeffrey P. Gambino ,  Shih-Fen Huang ,  Edward J. Nowak ,  Anthony K. Stamper

    发明人： Brent A. Anderson ,  Andres Bryant ,  William F. Clark, Jr. ,  Jeffrey P. Gambino ,  Shih-Fen Huang ,  Edward J. Nowak ,  Anthony K. Stamper

    IPC分类号： H01L27/088

    CPC分类号： H01L21/823412 ,  H01L21/823418 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/78

    摘要： In order to reduce power dissipation requirements, obtain full potential transistor performance and avoid power dissipation limitations on transistor performance in high density integrated circuits, transistors are operated in a sub-threshold (sub-Vth) or a near sub-Vth voltage regime (generally about 0.2 volts rather than a super-Vth regime of about 1.2 volts or higher) and optimized for such operation, particularly through simplification of the transistor structure, since intrinsic channel resistance is dominant in sub-Vth operating voltage regimes. Such simplifications include an underlap or recess of the source and drain regions from the gate which avoids overlap capacitance to partially recover loss of switching speed otherwise caused by low voltage operation, an ultra-thin gate structure having a thickness of 500 Å or less which also simplifies forming connections to the transistor and an avoidance of silicidation or alloy formation in the source, drain and/or gate of transistors.

    摘要翻译： 为了降低功耗要求，获得全电位晶体管性能，并避免在高密度集成电路中对晶体管性能的功耗限制，晶体管工作在亚阈值（sub-Vth）或接近sub-Vth电压方式 约0.2伏，而不是约1.2伏特或更高的超电压状态），并且为了这种操作而进行了优化，特别是通过简化晶体管结构，因为在Vth的工作电压方案中固有的沟道电阻是主要的。 这种简化包括来自栅极的源极和漏极区域的欠叠或凹陷，其避免重叠电容以部分恢复由低电压操作引起的切换速度的损失，厚度为或等于或小于500埃的超薄栅极结构 简化了与晶体管的形成连接，避免了晶体管的源极，漏极和/或栅极中的硅化或合金形成。

    Method of forming damascene filament wires
    3.
    发明授权
    Method of forming damascene filament wires 有权
    形成镶嵌长丝丝的方法

    公开(公告)号：US07915162B2

    公开(公告)日：2011-03-29

    申请号：US11839767

    申请日：2007-08-16

    申请人： Brent A. Anderson ,  Andres Bryant ,  Jeffrey P. Gambino ,  Anthony K. Stamper

    发明人： Brent A. Anderson ,  Andres Bryant ,  Jeffrey P. Gambino ,  Anthony K. Stamper

    IPC分类号： H01L21/44

    CPC分类号： H01L21/31144 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76835 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of forming a semiconductor device. A first dielectric layer is deposited on and in direct mechanical contact with the substrate. A first hard mask is deposited on the first dielectric layer. A first and second trench is formed within the first dielectric layer and the first hard mask. The second trench is wider than the first trench. A first conformal liner is deposited over the first hard mask and within the first and second trenches, a portion of which is removed, leaving a remaining portion of the first conformal liner in direct physical contact with the substrate, the first dielectric layer, and the first hard mask, and not on the first hard mask. Copper is deposited over the first conformal liner to overfill fill the first and second trenches and is planarized to remove an excess thereof to form a planar surface of the copper.

    摘要翻译： 一种形成半导体器件的方法。 第一电介质层沉积在衬底上并与衬底直接机械接触。 第一硬掩模沉积在第一介电层上。 第一和第二沟槽形成在第一介电层和第一硬掩模内。 第二沟槽比第一沟槽宽。 第一保形衬垫沉积在第一硬掩模之上并且在第一和第二沟槽内，其一部分被去除，留下第一保形衬垫的剩余部分与衬底，第一介电层和 第一个硬面罩，而不是在第一个硬面罩。 铜沉积在第一保形衬垫上以过满填充第一和第二沟槽，并被平坦化以除去其过量以形成铜的平坦表面。

    Pixel sensor cell with a dual work function gate electrode
    6.
    发明授权
    Pixel sensor cell with a dual work function gate electrode 有权
    具有双功能栅极电极的像素传感器单元

    公开(公告)号：US08580601B2

    公开(公告)日：2013-11-12

    申请号：US13571986

    申请日：2012-08-10

    申请人： Brent A. Anderson ,  Andres Bryant ,  William F. Clark, Jr. ,  John Joseph Ellis-Monaghan ,  Edward J. Nowak

    发明人： Brent A. Anderson ,  Andres Bryant ,  William F. Clark, Jr. ,  John Joseph Ellis-Monaghan ,  Edward J. Nowak

    IPC分类号： H01L21/00

    CPC分类号： H01L27/14614

    摘要： Pixel sensor cells, methods of fabricating pixel sensor cells, and design structures for a pixel sensor cell. The pixel sensor cell has a gate structure that includes a gate dielectric and a gate electrode on the gate dielectric. The gate electrode includes a layer with first and second sections that have a juxtaposed relationship on the gate dielectric. The second section of the gate electrode is comprised of a conductor, such as doped polysilicon or a metal. The first section of the gate electrode is comprised of a metal having a higher work function than the conductor comprising the second section so that the gate structure has an asymmetric threshold voltage.

    摘要翻译： 像素传感器单元，制造像素传感器单元的方法以及像素传感器单元的设计结构。 像素传感器单元具有在栅极电介质上包括栅极电介质和栅电极的栅极结构。 栅极电极包括具有在栅极电介质上具有并置关系的第一和第二部分的层。 栅电极的第二部分由诸如掺杂多晶硅或金属的导体组成。 栅电极的第一部分由具有比包括第二部分的导体更高的功函的金属组成，使得栅极结构具有非对称阈值电压。

    ASYMMETRIC FIELD EFFECT TRANSISTOR STRUCTURE AND METHOD
    8.
    发明申请
    ASYMMETRIC FIELD EFFECT TRANSISTOR STRUCTURE AND METHOD 有权
    不对称场效应晶体管结构与方法

    公开(公告)号：US20120168832A1

    公开(公告)日：2012-07-05

    申请号：US13246175

    申请日：2011-09-27

    申请人： Brent A. Anderson ,  Andres Bryant ,  William F. Clark, JR. ,  Edward J. Nowak

    发明人： Brent A. Anderson ,  Andres Bryant ,  William F. Clark, JR. ,  Edward J. Nowak

    IPC分类号： H01L29/78

    CPC分类号： H01L29/0847 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/78 ,  H01L29/7834 ,  H01L29/7835

    摘要： Disclosed are embodiments of an asymmetric field effect transistor structure and a method of forming the structure in which both series resistance in the source region (Rs) and gate to drain capacitance (Cgd) are reduced in order to provide optimal performance (i.e., to provide improved drive current with minimal circuit delay). Specifically, different heights of the source and drain regions and/or different distances between the source and drain regions and the gate are tailored to minimize series resistance in the source region (i.e., in order to ensure that series resistance is less than a predetermined resistance value) and in order to simultaneously to minimize gate to drain capacitance (i.e., in order to simultaneously ensure that gate to drain capacitance is less than a predetermined capacitance value).

    摘要翻译： 公开了非对称场效应晶体管结构的实施例和形成其中源极区（Rs）和栅极 - 漏极电容（Cgd）中的串联电阻都被降低以便提供最佳性能（即提供 改进的驱动电流，电路延迟最小）。 具体地说，源极和漏极区域的不同高度和/或源极和漏极区域与栅极之间的不同距离被调整以最小化源极区域中的串联电阻（即，为了确保串联电阻小于预定电阻 值），并且为了同时使栅极 - 漏极电容最小化（即，为了同时确保栅极到漏极电容小于预定的电容值）。

    Asymmetric field effect transistor structure and method
    9.
    发明授权
    Asymmetric field effect transistor structure and method 有权
    不对称场效应晶体管结构及方法

    公开(公告)号：US07843016B2

    公开(公告)日：2010-11-30

    申请号：US11869145

    申请日：2007-10-09

    申请人： Brent A. Anderson ,  Andres Bryant ,  William F. Clark, Jr. ,  Edward J. Nowak

    发明人： Brent A. Anderson ,  Andres Bryant ,  William F. Clark, Jr. ,  Edward J. Nowak

    IPC分类号： H01L29/78

    CPC分类号： H01L29/0847 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/78 ,  H01L29/7834 ,  H01L29/7835

    摘要： Disclosed are embodiments for a design structure of an asymmetric field effect transistor structure and a method of forming the structure in which both series resistance in the source region (Rs) and gate to drain capacitance (Cgd) are reduced in order to provide optimal performance (i.e., to provide improved drive current with minimal circuit delay). Specifically, different heights of the source and drain regions and/or different distances between the source and drain regions and the gate are tailored to minimize series resistance in the source region (i.e., in order to ensure that series resistance is less than a predetermined resistance value) and in order to simultaneously to minimize gate to drain capacitance (i.e., in order to simultaneously ensure that gate to drain capacitance is less than a predetermined capacitance value).

    摘要翻译： 公开了用于非对称场效应晶体管结构的设计结构的实施例以及形成其中源极区（Rs）和栅极 - 漏极电容（Cgd）中的串联电阻都被降低以便提供最佳性能（ 即，以最小的电路延迟来提供改进的驱动电流）。 具体地说，源极和漏极区域的不同高度和/或源极和漏极区域与栅极之间的不同距离被调整以最小化源极区域中的串联电阻（即，为了确保串联电阻小于预定电阻 值），并且为了同时使栅极 - 漏极电容最小化（即，为了同时确保栅极到漏极电容小于预定的电容值）。

    FULLY-DEPLETED LOW-BODY DOPING FIELD EFFECT TRANSISTOR (FET) WITH REVERSE SHORT CHANNEL EFFECTS (SCE) INDUCED BY SELF-ALIGNED EDGE BACK-GATE(S)
    10.
    发明申请
    FULLY-DEPLETED LOW-BODY DOPING FIELD EFFECT TRANSISTOR (FET) WITH REVERSE SHORT CHANNEL EFFECTS (SCE) INDUCED BY SELF-ALIGNED EDGE BACK-GATE(S) 有权
    具有反向短路通道效应（SCE）的全自动低体积场效应晶体管（FET）由自对准边缘背栅（S）

    公开(公告)号：US20090261415A1

    公开(公告)日：2009-10-22

    申请号：US12104683

    申请日：2008-04-17

    申请人： James W. Adkisson ,  Brent A. Anderson ,  Andres Bryant ,  William F. Clark, JR. ,  Edward J. Nowak

    发明人： James W. Adkisson ,  Brent A. Anderson ,  Andres Bryant ,  William F. Clark, JR. ,  Edward J. Nowak

    IPC分类号： H01L49/00 ,  H01L21/00

    CPC分类号： H01L29/78603 ,  H01L29/66621 ,  H01L29/78645 ,  H01L29/78648 ,  H01L29/78696

    摘要： Disclosed are embodiments of a field effect transistor (FET) and, more particularly, a fully-depleted, thin-body (FDTB) FET that allows for scaling with minimal short channel effects, such as drain induced barrier lowering (DIBL) and saturation threshold voltage (Vtsat) roll-off, at shorter channel lengths. The FDTB FET embodiments are configured with either an edge back-gate or split back-gate that can be biased in order to selectively adjust the potential barrier between the source/drain regions and the channel region for minimizing off-state leakage current between the drain region and the source region and/or for varying threshold voltage. These unique back-gate structures avoid the need for halo doping to ensure linear threshold voltage (Vtlin) roll-up at smaller channel lengths and, thus, avoid across-chip threshold voltage variations due to random doping fluctuations. Also disclosed are method embodiments for forming such FETs.

    摘要翻译： 公开了场效应晶体管（FET）的具体实施例，更具体地说，是允许以最小的短沟道效应（例如漏极感应势垒降低（DIBL）和饱和阈值））进行缩放的完全耗尽的薄体（FDTB）FET 电压（Vtsat）滚降，通道长度较短。 FDTB FET实施例配置有可被偏置的边缘背栅极或分支反向栅极，以便选择性地调节源极/漏极区域和沟道区域之间的势垒，以最小化漏极之间的截止状态漏电流 区域和源极区域和/或用于改变阈值电压。 这些独特的背栅结构避免了对光晕掺杂的需要，以确保较小通道长度的线性阈值电压（Vtlin）汇总，从而避免由于随机掺杂波动引起的跨芯片阈值电压变化。 还公开了用于形成这种FET的方法实施例。